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Date:   Fri, 15 Jan 2021 07:22:09 +0530
From:   Anshuman Khandual <anshuman.khandual@....com>
To:     Suzuki K Poulose <suzuki.poulose@....com>,
        linux-arm-kernel@...ts.infradead.org, coresight@...ts.linaro.org
Cc:     mathieu.poirier@...aro.org, mike.leach@...aro.org,
        Linu Cherian <lcherian@...vell.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 07/11] arm64: Add TRBE definitions



On 1/13/21 2:51 PM, Suzuki K Poulose wrote:
> On 1/13/21 4:18 AM, Anshuman Khandual wrote:
>> This adds TRBE related registers and corresponding feature macros.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@...aro.org>
>> Cc: Mike Leach <mike.leach@...aro.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@....com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@....com>
>> ---
>>   arch/arm64/include/asm/sysreg.h | 49 +++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 49 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 4acff97..d60750e7 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -329,6 +329,55 @@
>>     /*** End of Statistical Profiling Extension ***/
>>   +/*
>> + * TRBE Registers
>> + */
>> +#define SYS_TRBLIMITR_EL1        sys_reg(3, 0, 9, 11, 0)
>> +#define SYS_TRBPTR_EL1            sys_reg(3, 0, 9, 11, 1)
>> +#define SYS_TRBBASER_EL1        sys_reg(3, 0, 9, 11, 2)
>> +#define SYS_TRBSR_EL1            sys_reg(3, 0, 9, 11, 3)
>> +#define SYS_TRBMAR_EL1            sys_reg(3, 0, 9, 11, 4)
>> +#define SYS_TRBTRG_EL1            sys_reg(3, 0, 9, 11, 6)
>> +#define SYS_TRBIDR_EL1            sys_reg(3, 0, 9, 11, 7)
>> +
>> +#define TRBLIMITR_LIMIT_MASK        GENMASK_ULL(51, 0)
>> +#define TRBLIMITR_LIMIT_SHIFT        12
>> +#define TRBLIMITR_NVM            BIT(5)
>> +#define TRBLIMITR_TRIG_MODE_MASK    GENMASK(1, 0)
>> +#define TRBLIMITR_TRIG_MODE_SHIFT    2
> 
> This must be 3.

Changed.

> 
> Rest looks fine to me
> 
> Suzuki

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