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Message-ID: <161067651323.3661239.14709087785393568909@swboyd.mtv.corp.google.com>
Date: Thu, 14 Jan 2021 18:08:33 -0800
From: Stephen Boyd <swboyd@...omium.org>
To: Douglas Anderson <dianders@...omium.org>,
Jason Cooper <jason@...edaemon.net>,
Linus Walleij <linus.walleij@...aro.org>,
Marc Zyngier <maz@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>
Cc: Neeraj Upadhyay <neeraju@...eaurora.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rajendra Nayak <rnayak@...eaurora.org>,
Srinivas Ramana <sramana@...eaurora.org>,
linux-arm-msm@...r.kernel.org, Maulik Shah <mkshah@...eaurora.org>,
linux-gpio@...r.kernel.org,
Douglas Anderson <dianders@...omium.org>,
Andy Gross <agross@...nel.org>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 4/4] pinctrl: qcom: Don't clear pending interrupts when enabling
Quoting Douglas Anderson (2021-01-14 15:40:27)
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 192ed31eabf4..712a693425fc 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -1097,16 +1128,11 @@ static int msm_gpio_irq_reqres(struct irq_data *d)
> }
>
> /*
> - * Clear the interrupt that may be pending before we enable
> - * the line.
> - * This is especially a problem with the GPIOs routed to the
> - * PDC. These GPIOs are direct-connect interrupts to the GIC.
> - * Disabling the interrupt line at the PDC does not prevent
> - * the interrupt from being latched at the GIC. The state at
> - * GIC needs to be cleared before enabling.
> + * The disable / clear-enable workaround we do in msm_pinmux_set_mux()
> + * only works if disable is not lazy since we only clear any bogus
> + # interrupt in hardware. Explicitly mark the interrupt as UNLAZY.
Ah! What is # doing there?
> */
> - if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
> - irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0);
> + irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY);
>
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