lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Sat, 16 Jan 2021 11:27:39 +0800 From: Zhen Lei <thunder.leizhen@...wei.com> To: Russell King <rmk+kernel@....linux.org.uk>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Will Deacon <will.deacon@....com>, "Haojian Zhuang" <haojian.zhuang@...il.com>, Arnd Bergmann <arnd@...db.de>, Rob Herring <robh+dt@...nel.org>, Wei Xu <xuwei5@...ilicon.com>, devicetree <devicetree@...r.kernel.org>, linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>, linux-kernel <linux-kernel@...r.kernel.org> CC: Zhen Lei <thunder.leizhen@...wei.com> Subject: [PATCH v5 3/4] dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller Add devicetree binding for Hisilicon Kunpeng L3 cache controller. Signed-off-by: Zhen Lei <thunder.leizhen@...wei.com> --- .../arm/hisilicon/kunpeng-l3cache.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml new file mode 100644 index 000000000000000..5bf33c0e4d14b7f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/kunpeng-l3cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Kunpeng L3 cache controller + +maintainers: + - Wei Xu <xuwei5@...ilicon.com> + +description: | + The Hisilicon Kunpeng L3 outer cache controller supports a maximum of 36-bit + physical addresses. The data cached in the L3 outer cache can be operated + based on the physical address range or the entire cache. + +properties: + compatible: + items: + - enum: + - hisilicon,kunpeng506-l3cache + - hisilicon,kunpeng509-l3cache + - const: hisilicon,kunpeng-l3cache + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + l3cache@...2b000 { + compatible = "hisilicon,kunpeng509-l3cache", "hisilicon,kunpeng-l3cache"; + reg = <0xf302b000 0x1000>; + }; +... -- 2.26.0.106.g9fadedd
Powered by blists - more mailing lists