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Message-ID: <CAAfSe-u2vr-jbrVe3sfC470=y+=Dc=vffUSS-+gm1cfGnkW=OA@mail.gmail.com>
Date: Mon, 18 Jan 2021 14:58:15 +0800
From: Chunyan Zhang <zhang.lyra@...il.com>
To: Mike Leach <mike.leach@...aro.org>
Cc: Mathieu Poirier <mathieu.poirier@...aro.org>,
Suzuki K Poulose <suzuki.poulose@....com>,
Coresight ML <coresight@...ts.linaro.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Chunyan Zhang <chunyan.zhang@...soc.com>,
Bin Ji <bin.ji@...soc.com>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75
On Fri, 15 Jan 2021 at 18:18, Mike Leach <mike.leach@...aro.org> wrote:
>
> Hi Chunyan,
>
> On Fri, 15 Jan 2021 at 08:39, Chunyan Zhang <zhang.lyra@...il.com> wrote:
> >
> > From: Bin Ji <bin.ji@...soc.com>
> >
> > Add ETM amba id to support Cortex-A55(Ananke) and Cortex-A75(Promethus).
> >
> > Signed-off-by: Bin Ji <bin.ji@...soc.com>
> > Signed-off-by: Chunyan Zhang <chunyan.zhang@...soc.com>
> > ---
> > drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index b20b6ff17cf6..66c6641c71ea 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -1709,9 +1709,11 @@ static int etm4_remove(struct amba_device *adev)
> >
> > static const struct amba_id etm4_ids[] = {
> > CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
> > + CS_AMBA_ID(0x000bbd05), /* Cortex-A55 */
>
> Use AMBA_UCI_ID(). See UCI comment below.
>
> > CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
> > CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
> > CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
> > + CS_AMBA_ID(0x000bbd0a), /* Cortex-A75 */
>
> This AMBA ID is used for PMU, ETM, debug block and CTI for this core.
> Please use the CS_AMBA_UCI_ID macro to correctly identify this
> component.
> See CoreSight 3.0 Architecture Manual 3.0 (IHI 0029E) section B2.1.2
> for an explanation of UCI.
Thanks Mike.
I just sent out a new version addressing your comments.
Chunyan
>
> Regards
>
> Mike
>
>
>
> > CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
> > CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
> > CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
> > --
> > 2.25.1
> >
> > _______________________________________________
> > CoreSight mailing list
> > CoreSight@...ts.linaro.org
> > https://lists.linaro.org/mailman/listinfo/coresight
>
>
>
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK
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