linux-kernel - [PATCH v3 1/2] rtc: pcf2127: Disable Power-On Reset Override

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Message-Id: <20210118085752.5759-2-p.rosenberger@kunbus.com>
Date:   Mon, 18 Jan 2021 09:57:51 +0100
From:   Philipp Rosenberger <p.rosenberger@...bus.com>
To:     a.zummo@...ertech.it, alexandre.belloni@...tlin.com
Cc:     p.rosenberger@...bus.com, dan.carpenter@...cle.com,
        u.kleine-koenig@...gutronix.de, biwen.li@....com, lvb@...hos.com,
        bruno.thomsen@...il.com, l.sanfilippo@...bus.com,
        linux-rtc@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH v3 1/2] rtc: pcf2127: Disable Power-On Reset Override

To resume normal operation after a total power loss (no or empty
battery) the "Power-On Reset Override (PORO)" facility needs to be
disabled.

The register reset value sets the PORO enabled and the data sheet
recommends setting it to disabled for normal operation.

>From what I've seen on the PCF2127 and PCF2129 there is not
interrupted gernerated at the interrupt pin (INT), as long the PORO bit
is set. This behavior is not documented in the manual.

Signed-off-by: Philipp Rosenberger <p.rosenberger@...bus.com>
---
 drivers/rtc/rtc-pcf2127.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 39a7b5116aa4..0e06907d3ddc 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -26,6 +26,7 @@
 
 /* Control register 1 */
 #define PCF2127_REG_CTRL1		0x00
+#define PCF2127_BIT_CTRL1_POR_OVRD		BIT(3)
 #define PCF2127_BIT_CTRL1_TSF1			BIT(4)
 /* Control register 2 */
 #define PCF2127_REG_CTRL2		0x01
@@ -612,6 +613,13 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap,
 		ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
 	}
 
+	/*
+	 * The "Power-On Reset Override" facility prevents the RTC to do a reset
+	 * after power on. For normal operation the PORO must be disabled.
+	 */
+	regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
+				PCF2127_BIT_CTRL1_POR_OVRD);
+
 	/*
 	 * Watchdog timer enabled and reset pin /RST activated when timed out.
 	 * Select 1Hz clock source for watchdog timer.
-- 
2.29.2