lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <87r1miuv2h.fsf@kernel.org>
Date:   Mon, 18 Jan 2021 17:24:38 +0200
From:   Felipe Balbi <balbi@...nel.org>
To:     Michael Grzeschik <mgr@...gutronix.de>,
        Manish Narani <manish.narani@...inx.com>
Cc:     gregkh@...uxfoundation.org, robh+dt@...nel.org,
        michal.simek@...inx.com, p.zabel@...gutronix.de,
        devicetree@...r.kernel.org, linux-usb@...r.kernel.org,
        linux-kernel@...r.kernel.org, git@...inx.com,
        linux-arm-kernel@...ts.infradead.org, kernel@...gutronix.de
Subject: Re: [RESEND PATCH v3 2/2] usb: dwc3: Add driver for Xilinx platforms


Hi,

Michael Grzeschik <mgr@...gutronix.de> writes:
> On Tue, Dec 15, 2020 at 12:24:51PM +0530, Manish Narani wrote:
>>Add a new driver for supporting Xilinx platforms. This driver is used
>>for some sequence of operations required for Xilinx USB controllers.
>>This driver is also used to choose between PIPE clock coming from SerDes
>>and the Suspend Clock. Before the controller is out of reset, the clock
>>selection should be changed to PIPE clock in order to make the USB
>>controller work. There is a register added in Xilinx USB controller
>>register space for the same.
>
> I tried out this driver with the vanilla kernel on an zynqmp. Without
> this patch the USB-Gadget is already acting buggy. In the gadget mode,
> some iterations of plug/unplug results to an stalled gadget which will
> never come back without a reboot.
>
> With the corresponding code of this driver (reset assert, clk modify,
> reset deassert) in the downstream kernels phy driver we found out it is
> totaly stable. But using this exact glue driver which should do the same
> as the downstream code, the gadget still was buggy the way described
> above.
>
> I suspect the difference lays in the different order of operations.
> While the downstream code is runing the resets inside the phy driver
> which is powered and initialized in the dwc3-core itself. With this glue
> layser approach of this patch the whole phy init is done before even
> touching dwc3-core in any way. It seems not to have the same effect,
> though.
>
> If really the order of operations is limiting us, we probably need
> another solution than this glue layer. Any Ideas?

might be a good idea to collect dwc3 trace events. Can you do that?

-- 
balbi

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ