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Message-ID: <20210118153226.3qthltiknhjggdlq@gilmour>
Date:   Mon, 18 Jan 2021 16:32:26 +0100
From:   Maxime Ripard <maxime@...no.tech>
To:     Andre Przywara <andre.przywara@....com>
Cc:     Chen-Yu Tsai <wens@...e.org>,
        Jernej Skrabec <jernej.skrabec@...l.net>,
        Icenowy Zheng <icenowy@...c.io>,
        Linus Walleij <linus.walleij@...aro.org>,
        Rob Herring <robh@...nel.org>,
        Clément Péron <peron.clem@...il.com>,
        Samuel Holland <samuel@...lland.org>,
        Shuosheng Huang <huangshuosheng@...winnertech.com>,
        Yangtao Li <tiny.windzz@...il.com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-sunxi@...glegroups.com,
        Kishon Vijay Abraham I <kishon@...com>,
        Vinod Koul <vkoul@...nel.org>
Subject: Re: [PATCH v3 13/21] phy: sun4i-usb: Rework HCI PHY (aka.
 "pmu_unk1") handling

On Mon, Jan 18, 2021 at 02:08:40AM +0000, Andre Przywara wrote:
> As Icenowy pointed out, newer manuals (starting with H6) actually
> document the register block at offset 0x800 as "HCI controller and PHY
> interface", also describe the bits in our "PMU_UNK1" register.
> Let's put proper names to those "unknown" variables and symbols.
> 
> While we are at it, generalise the existing code by allowing a bitmap
> of bits to clear, to cover newer SoCs: The A100 and H616 use a different
> bit for the SIDDQ control.
> 
> Signed-off-by: Andre Przywara <andre.przywara@....com>

Acked-by: Maxime Ripard <mripard@...nel.org>

maxime

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