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Message-ID: <20210119143412.GD17369@gaia>
Date: Tue, 19 Jan 2021 14:34:13 +0000
From: Catalin Marinas <catalin.marinas@....com>
To: Vincenzo Frascino <vincenzo.frascino@....com>
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
kasan-dev@...glegroups.com, Will Deacon <will@...nel.org>,
Dmitry Vyukov <dvyukov@...gle.com>,
Andrey Ryabinin <aryabinin@...tuozzo.com>,
Alexander Potapenko <glider@...gle.com>,
Marco Elver <elver@...gle.com>,
Evgenii Stepanov <eugenis@...gle.com>,
Branislav Rankov <Branislav.Rankov@....com>,
Andrey Konovalov <andreyknvl@...gle.com>
Subject: Re: [PATCH v4 4/5] arm64: mte: Enable async tag check fault
On Mon, Jan 18, 2021 at 06:30:32PM +0000, Vincenzo Frascino wrote:
> static void update_sctlr_el1_tcf0(u64 tcf0)
> {
> /* ISB required for the kernel uaccess routines */
> @@ -235,6 +273,15 @@ void mte_thread_switch(struct task_struct *next)
> /* avoid expensive SCTLR_EL1 accesses if no change */
> if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0)
> update_sctlr_el1_tcf0(next->thread.sctlr_tcf0);
> +
> + /*
> + * Check if an async tag exception occurred at EL1.
> + *
> + * Note: On the context switch path we rely on the dsb() present
> + * in __switch_to() to guarantee that the indirect writes to TFSR_EL1
> + * are synchronized before this point.
> + */
> + mte_check_tfsr_el1();
> }
We need an isb() before mte_check_tfsr_el1() here as well, we only have
a dsb() in __switch_to(). We do have an isb() in update_sctlr_el1_tcf0()
but only if the check passed. Now, it's worth benchmarking how expensive
update_sctlr_el1_tcf0() is (i.e. an SCTLR_EL1 access + isb with
something like hackbench) and we could probably remove the check
altogether. In the meantime, you can add an isb() on the "else" path of
the above check.
--
Catalin
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