linux-kernel - Re: [PATCH v3] clk: sunxi-ng: h6: Fix clock divider range on some clocks

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Message-ID: <20210120095946.nljah6r3e4qhxdup@gilmour>
Date:   Wed, 20 Jan 2021 10:59:46 +0100
From:   Maxime Ripard <maxime@...no.tech>
To:     Andre Przywara <andre.przywara@....com>
Cc:     Chen-Yu Tsai <wens@...e.org>,
        Jernej Skrabec <jernej.skrabec@...l.net>,
        Icenowy Zheng <icenowy@...c.io>,
        Samuel Holland <samuel@...lland.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-sunxi@...glegroups.com
Subject: Re: [PATCH v3] clk: sunxi-ng: h6: Fix clock divider range on some
 clocks

On Mon, Jan 18, 2021 at 12:09:12AM +0000, Andre Przywara wrote:
> While comparing clocks between the H6 and H616, some of the M factor
> ranges were found to be wrong: the manual says they are only covering
> two bits [1:0], but our code had "5" in the number-of-bits field.
> 
> By writing 0xff into that register in U-Boot and via FEL, it could be
> confirmed that bits [4:2] are indeed masked off, so the manual is right.
> 
> Change to number of bits in the affected clock's description.
> 
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
> Signed-off-by: Andre Przywara <andre.przywara@....com>
> Reviewed-by: Jernej Skrabec <jernej.skrabec@...l.net>

Applied, thanks
Maxime

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