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Date:   Wed, 20 Jan 2021 04:23:53 +0300
From:   Dmitry Osipenko <>
To:     Thierry Reding <>,
        Jonathan Hunter <>,
        Peter Geis <>,
        Nicolas Chauvet <>,
        Matt Merhar <>
Subject: [PATCH v3 1/5] soc/tegra: pmc: Fix imbalanced clock disabling in error code path

The tegra_powergate_power_up() has a typo in the error code path where it
will try to disable clocks twice, fix it. In practice that error never
happens, so this is a minor correction.

Tested-by: Peter Geis <> # Ouya T30
Tested-by: Nicolas Chauvet <> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <> # Ouya T30
Tested-by: Dmitry Osipenko <> # A500 T20 and Nexus7 T30
[this patch was also boot-tested on some other T20/30/114 devices]
Signed-off-by: Dmitry Osipenko <>
 drivers/soc/tegra/pmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index df9a5ca8c99c..fd2ba3c59178 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -638,7 +638,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
 	err = tegra_powergate_enable_clocks(pg);
 	if (err)
-		goto disable_clks;
+		goto powergate_off;
 	usleep_range(10, 20);

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