linux-kernel - Re: [PATCH v4] drivers/soc/litex: Add restart handler

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Message-ID: <20210120130659.GN2002709@lianli.shorne-pla.net>
Date:   Wed, 20 Jan 2021 22:06:59 +0900
From:   Stafford Horne <shorne@...il.com>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Karol Gugala <kgugala@...micro.com>,
        Mateusz Holenko <mholenko@...micro.com>,
        Gabriel Somlo <gsomlo@...il.com>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Joel Stanley <joel@....id.au>
Subject: Re: [PATCH v4] drivers/soc/litex: Add restart handler

On Wed, Jan 20, 2021 at 09:20:39AM +0100, Geert Uytterhoeven wrote:
> Hi Stafford,
> 
> On Tue, Jan 19, 2021 at 11:11 PM Stafford Horne <shorne@...il.com> wrote:
> > On Wed, Jan 20, 2021 at 06:34:44AM +0900, Stafford Horne wrote:
> > > On Tue, Jan 19, 2021 at 09:09:38AM +0100, Geert Uytterhoeven wrote:
> > > > Let the LiteX SoC Controller register a restart handler, which resets
> > > > the LiteX SoC by writing 1 to CSR_CTRL_RESET_ADDR.
> > > >
> > > > Signed-off-by: Geert Uytterhoeven <geert@...ux-m68k.org>
> > >
> > > Thanks, this looks good to me, queued to my linux-next branch.
> > >
> > > -Stafford
> > >
> > > > @@ -66,8 +71,19 @@ static int litex_check_csr_access(void __iomem *reg_addr)
> > > >
> > > >  struct litex_soc_ctrl_device {
> > > >     void __iomem *base;
> > > > +   struct notifier_block reset_nb;
> > > >  };
> > > >
> > > > +static int litex_reset_handler(struct notifier_block *this, unsigned long mode,
> > > > +                          void *cmd)
> > > > +{
> > > > +   struct litex_soc_ctrl_device *soc_ctrl_dev =
> > > > +           container_of(this, struct litex_soc_ctrl_device, reset_nb);
> > >
> > > Nice.
> > >
> > > > +   litex_write32(soc_ctrl_dev->base + RESET_REG_OFF, RESET_REG_VALUE);
> > > > +   return NOTIFY_DONE;
> > > > +}
> > > > +
> >
> > Actually, I tested this out on the latest (2-weeks ago) Litex and
> > openrisc/for-next and it didn't seem to work correctly.
> >
> > I will look into it a bit closer, but if you see or can think of anything let
> > me know.  Note There are a few failures below related to network services as my
> > for-next kernel doesnt have a network driver (yet).
> 
> Hmmm, openrisc/for-next does have commit 131172a4a8ce3fcc ("openrisc:
> restart: Call common handlers before hanging").
> 
> It's been a few years I used an OpenRISC setup.
> Do you have a link to Linux on mor1kx/LiteX setup instructions?

Actually, I rebuilt everything again and it works fine.  FYI, my instructions
for setup are here:

 - https://github.com/stffrdhrn/or1k-utils/tree/master/litex

I use an arty dev board, you can see the reset working below. There are some
things I need to fix in my dev rootfs shutdown scripts but it does reset.


    # shutdown -r now

    Broadcast message from root@...ldroot (console) (Thu Jan  1 00:01:07 1970):
    The system is going down for reboot NOW!
    INIT: Switching to runlevel: 6
    # mounting home work nfs ...
    mount: mounting 10.0.0.27:/home/shorne/work on /home/shorne/work failed: No such device
    enabling login for shorne ...
    setting coredumps ...
    Stopping dropbear sshd: FAIL
    Stopping ntpd: FAIL
    Nothing to do, sntp is not a daemon.
    Stopping network: ifdown: interface lo not configured
    ifdown: interface eth0 not configured
    OK
    Saving random seed: [   70.960000] random: dd: uninitialized urandom read (512 bytes read)
    OK
    Stopping klogd: OK
    Stopping syslogd: start-stop-daemon: warning: killing process 51: No such
    process
    FAIL
    umount: devtmpfs busy - remounted read-only
    umount: can't unmount /: Invalid argument
    [   72.650000] reboot: Res
	    __   _ __      _  __
	   / /  (_) /____ | |/_/
	  / /__/ / __/ -_)>  <
	 /____/_/\__/\__/_/|_|
       Build your hardware, easily!

     (c) Copyright 2012-2020 Enjoy-Digital
     (c) Copyright 2007-2015 M-Labs

     BIOS built on Jan 20 2021 21:18:10
     BIOS CRC passed (b12f1de3)

     Migen git sha1: 40b1092
     LiteX git sha1: 57289dd4

    --=============== SoC ==================--
    CPU:            MOR1KX @ 100MHz
    BUS:            WISHBONE 32-bit @ 4GiB

-Stafford