linux-kernel - Re: [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors

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Message-ID: <195e2bfe3a5e5503d9988b517159300e@kernel.org>
Date:   Thu, 21 Jan 2021 16:25:54 +0000
From:   Marc Zyngier <maz@...nel.org>
To:     Mohamed Mediouni <mohamed.mediouni@...amail.com>
Cc:     Will Deacon <will@...nel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Mark Rutland <mark.rutland@....com>,
        Hector Martin <marcan@...can.st>, linux-kernel@...r.kernel.org,
        Stan Skowronek <stan@...ellium.com>
Subject: Re: [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple
 processors

On 2021-01-21 15:12, Mohamed Mediouni wrote:
> Please ignore that patch.
> 
> It turns out that the PCIe controller on Apple M1 expects posted
> writes and so the memory range for it ought to be set nGnRE.
> So, we need to use nGnRnE for on-chip MMIO and nGnRE for PCIe BARs.
> 
> The MAIR approach isn’t adequate for such a thing, so we’ll have to
> look elsewhere.

Well, there isn't many alternative to having a memory type defined
in MAIR if you want to access your PCIe devices with specific
semantics.

It probably means defining a memory type for PCI only, but:
- we only have a single free MT entry, and I'm not sure we can
   afford to waste this on a specific platform (can we re-purpose
   GRE instead?),
- we'd need to teach the PCI code to use this...

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...