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Message-Id: <cover.1611206601.git.sudaraja@codeaurora.org>
Date:   Wed, 20 Jan 2021 21:29:12 -0800
From:   Sudarshan Rajagopalan <sudaraja@...eaurora.org>
To:     linux-mm@...ck.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Anshuman Khandual <anshuman.khandual@....com>,
        David Hildenbrand <david@...hat.com>
Cc:     Sudarshan Rajagopalan <sudaraja@...eaurora.org>
Subject: [PATCH 0/1] arm64/sparsemem: reduce SECTION_SIZE_BITS

This patch is the follow-up from the discussions in the thread [1].
Reducing the section size has the merit of reducing wastage of reserved memory
for vmmemmap mappings for sections with large memory holes. Also with smaller 
section size gives more grunularity and agility for memory hot(un)plugging.

But there are also constraints in reducing SECTION_SIZE_BIT:

- Should accommodate highest order page for a given config
- Should not break PMD mapping in vmemmap for 4K pages
- Should not consume too many page->flags bits reducing space for other info

This patch uses the suggestions from Anshuman Khandual and David Hildenbrand
in thread [1] to set the least possible section size to 128MB for 4K and 16K
base page size configs for simplicity, and to 512MB for 64K base page size config.

[1] https://lore.kernel.org/lkml/cover.1609895500.git.sudaraja@codeaurora.org/T/#m8ee60ae69db5e9eb06ca7999c43828d49ccb9626


Sudarshan Rajagopalan (1):
  arm64/sparsemem: reduce SECTION_SIZE_BITS

 arch/arm64/include/asm/sparsemem.h | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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