linux-kernel - Re: [v7,1/2] dt-binding: reset-controller: mediatek: add YAML schemas

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <CAATdQgA5pKhjOf5gxo+h7cs7kCts3DeKGU5axeX2t+OaJFHyBg@mail.gmail.com>
Date:   Fri, 22 Jan 2021 16:13:32 +0800
From:   Ikjoon Jang <ikjn@...omium.org>
To:     Crystal Guo <crystal.guo@...iatek.com>
Cc:     p.zabel@...gutronix.de, Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        open list <linux-kernel@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Stanley Chu (朱原陞) 
        <stanley.chu@...iatek.com>,
        srv_heupstream <srv_heupstream@...iatek.com>,
        Seiya Wang (王迺君) 
        <seiya.wang@...iatek.com>,
        Fan Chen (陳凡) <fan.chen@...iatek.com>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@...ts.infradead.org>,
        Yingjoe Chen <Yingjoe.Chen@...iatek.com>, s-anna@...com,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-arm-kernel@...ts.infradead.org>, Yidi.Lin@...iatek.com
Subject: Re: [v7,1/2] dt-binding: reset-controller: mediatek: add YAML schemas

On Fri, Jan 15, 2021 at 7:23 PM Crystal Guo <crystal.guo@...iatek.com> wrote:
>
> Add a YAML documentation for Mediatek, which uses ti reset-controller
> driver directly. The TI reset controller provides a common reset
> management, and is suitable for Mediatek SoCs.
>
> Signed-off-by: Crystal Guo <crystal.guo@...iatek.com>
> ---
>  .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++
>  1 file changed, 51 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
>
> diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> new file mode 100644
> index 000000000000..85d241cdb0ea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Reset Controller
> +
> +maintainers:
> +  - Crystal Guo <crystal.guo@...iatek.com>
> +
> +description:
> +  The bindings describe the reset-controller for Mediatek SoCs,
> +  which is based on TI reset controller. For more detail, please
> +  visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
> +
> +properties:
> +  compatible:
> +    const: mediatek,syscon-reset
> +
> +  '#reset-cells':
> +    const: 1
> +
> +  ti,reset-bits:
> +    description: >
> +      Contains the reset control register information, please refer to
> +      Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
> +

I remember that Rob didn't like adding new users of this property,

How about removing this from here and using a hardcoded version of
register layouts into driver code (and match it with compatible) ?

e.g.
struct ti_syscon_reset_data mt8192_reset_data { ... }

> +required:
> +  - compatible
> +  - '#reset-cells'
> +  - ti,reset-bits
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/reset/ti-syscon.h>
> +    infracfg: infracfg@...01000 {
> +        compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> +        reg = <0 0x10001000>;
> +        #clock-cells = <1>;
> +
> +        infracfg_rst: reset-controller {
> +            compatible = "mediatek,syscon-reset";
> +            #reset-cells = <1>;
> +            ti,reset-bits = <
> +               0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
> +            >;
> +        };
> +    };
> --
> 2.18.0
>