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Message-ID: <CALCETrWPnvNr9S2hsxL+pbhNWv0OOL7tBq1XmABPjYK7zZSJbw@mail.gmail.com>
Date: Sun, 24 Jan 2021 18:24:42 -0800
From: Andy Lutomirski <luto@...nel.org>
To: Lai Jiangshan <jiangshanlai@...il.com>
Cc: LKML <linux-kernel@...r.kernel.org>,
Lai Jiangshan <laijs@...ux.alibaba.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
X86 ML <x86@...nel.org>, "H. Peter Anvin" <hpa@...or.com>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Andy Lutomirski <luto@...nel.org>,
Peter Zijlstra <peterz@...radead.org>,
Al Viro <viro@...iv.linux.org.uk>,
Sasha Levin <sashal@...nel.org>,
Vincenzo Frascino <vincenzo.frascino@....com>,
Joerg Roedel <jroedel@...e.de>,
Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>,
Reinette Chatre <reinette.chatre@...el.com>,
"Chang S. Bae" <chang.seok.bae@...el.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Gabriel Krisman Bertazi <krisman@...labora.com>,
Kees Cook <keescook@...omium.org>,
Frederic Weisbecker <frederic@...nel.org>,
Jens Axboe <axboe@...nel.dk>, Andi Kleen <ak@...ux.intel.com>,
Mike Rapoport <rppt@...nel.org>, Mike Hommey <mh@...ndium.org>,
Mark Gross <mgross@...ux.intel.com>,
Fenghua Yu <fenghua.yu@...el.com>,
Tony Luck <tony.luck@...el.com>,
Anthony Steinhauser <asteinhauser@...gle.com>,
Jay Lang <jaytlang@....edu>
Subject: Re: [PATCH] x86_64: move cpu_current_top_of_stack out of TSS
On Fri, Jan 22, 2021 at 11:48 PM Lai Jiangshan <jiangshanlai@...il.com> wrote:
>
> From: Lai Jiangshan <laijs@...ux.alibaba.com>
>
> When X86_BUG_CPU_MELTDOWN & KPTI, cpu_current_top_of_stack lives in the
> TSS which is also in the user CR3 and it becomes a coveted fruit. An
> attacker can fetch the kernel stack top from it and continue next steps
> of actions based on the kernel stack.
>
> The address might not be very usefull for attacker, but it is not so
> necessary to be in TSS either. It is only accessed when CR3 is kernel CR3
> and gs_base is kernel gs_base which means it can be in any percpu variable.
>
> The major reason it is in TSS might be performance because it is hot in
> cache and tlb since we just access sp2 as the scratch space in syscall.
>
> So we can move it to a percpu variable near other hot percpu variables,
> such as current_task, __preempt_count, and they are in the same
> cache line.
>
> tools/testing/selftests/seccomp/seccomp_benchmark desn't show any
> performance lost in "getpid native" result. And actually, the result
> changes from 93ns before patch to 92ns after patch when !KPTI, and the
> test is very stable although the test desn't show a higher degree of
> precision but enough to know it doesn't cause degression for the test.
I'm okay with this concept, and it's a decent cleanup. But the patch
is incomplete. There are a whole bunch of other sp1 users in
arch/x86, and we should get rid of all of them at once. Most notably,
the 32-bit code uses both the percpu variable and sp1 right now, and
that should be cleaned up. (It's also quite obfuscated in the current
code.)
See below for minor additional comments.
>
> Signed-off-by: Lai Jiangshan <laijs@...ux.alibaba.com>
> ---
> arch/x86/include/asm/processor.h | 10 ----------
> arch/x86/include/asm/switch_to.h | 7 +------
> arch/x86/include/asm/thread_info.h | 6 ------
> arch/x86/kernel/cpu/common.c | 3 +++
> arch/x86/kernel/process.c | 8 ++------
> arch/x86/mm/pti.c | 7 +++----
> 6 files changed, 9 insertions(+), 32 deletions(-)
>
> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
> index c20a52b5534b..886d32da1318 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -314,11 +314,6 @@ struct x86_hw_tss {
> struct x86_hw_tss {
> u32 reserved1;
> u64 sp0;
> -
> - /*
> - * We store cpu_current_top_of_stack in sp1 so it's always accessible.
> - * Linux does not use ring 1, so sp1 is not otherwise needed.
> - */
> u64 sp1;
>
> /*
> @@ -428,12 +423,7 @@ struct irq_stack {
>
> DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
>
> -#ifdef CONFIG_X86_32
> DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
> -#else
> -/* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
> -#define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
> -#endif
>
> #ifdef CONFIG_X86_64
> struct fixed_percpu_data {
> diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h
> index 9f69cc497f4b..4f0bc8533a54 100644
> --- a/arch/x86/include/asm/switch_to.h
> +++ b/arch/x86/include/asm/switch_to.h
> @@ -71,12 +71,7 @@ static inline void update_task_stack(struct task_struct *task)
> else
> this_cpu_write(cpu_tss_rw.x86_tss.sp1, task->thread.sp0);
> #else
> - /*
> - * x86-64 updates x86_tss.sp1 via cpu_current_top_of_stack. That
> - * doesn't work on x86-32 because sp1 and
> - * cpu_current_top_of_stack have different values (because of
> - * the non-zero stack-padding on 32bit).
> - */
> + /* XENPV keeps its entry stack to be kernel stack. */
How about:
Xen PV enters the kernel on the thread stack.
> if (static_cpu_has(X86_FEATURE_XENPV))
> load_sp0(task_top_of_stack(task));
> #endif
> diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
> index 0d751d5da702..3dc93d8df425 100644
> --- a/arch/x86/include/asm/thread_info.h
> +++ b/arch/x86/include/asm/thread_info.h
> @@ -197,12 +197,6 @@ static inline int arch_within_stack_frames(const void * const stack,
> #endif
> }
>
> -#else /* !__ASSEMBLY__ */
> -
> -#ifdef CONFIG_X86_64
> -# define cpu_current_top_of_stack (cpu_tss_rw + TSS_sp1)
A complete patch would also remove TSS_sp1 from asm-offsets.
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