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Message-Id: <20210125180427.3109269-1-iskren.chernev@gmail.com>
Date: Mon, 25 Jan 2021 20:04:24 +0200
From: Iskren Chernev <iskren.chernev@...il.com>
To: Bjorn Andersson <bjorn.andersson@...aro.org>
Cc: Andy Gross <agross@...nel.org>, Rob Herring <robh+dt@...nel.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Iskren Chernev <iskren.chernev@...il.com>,
Samuel Pascua <pascua.samuel.14@...il.com>,
Alexey Minnekhanov <alexeymin@...tmarketos.org>,
Brian Masney <masneyb@...tation.org>,
phone-devel@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht
Subject: [PATCH v3 1/4] ARM: dts: qcom: msm8974: add gpu support
From: Brian Masney <masneyb@...tation.org>
Add support for the a3xx GPU. opp_table is chosen to include lower
frequencies common to all different msm8974 variants.
Signed-off-by: Brian Masney <masneyb@...tation.org>
[iskren.chernev@...il.com: change opp-table values in v3]
Signed-off-by: Iskren Chernev <iskren.chernev@...il.com>
---
Changes in v3:
- change opp-table as suggested by Konrad Dybcio
- remove tested-by/reviewed-by because of code changes
v2: https://lkml.org/lkml/2021/1/24/142
v1: https://lkml.org/lkml/2020/12/30/322
arch/arm/boot/dts/qcom-msm8974.dtsi | 45 +++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 51f5f904f9eb9..683622d6c8954 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1399,6 +1399,51 @@ cnoc: interconnect@...80000 {
<&rpmcc RPM_SMD_CNOC_A_CLK>;
};
+ gpu_opp_table: opp_table {
+ status = "disabled";
+
+ compatible = "operating-points-v2";
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+
+ opp-27000000 {
+ opp-hz = /bits/ 64 <27000000>;
+ };
+ };
+
+ gpu: adreno@...00000 {
+ status = "disabled";
+
+ compatible = "qcom,adreno-330.2",
+ "qcom,adreno";
+ reg = <0xfdb00000 0x10000>;
+ reg-names = "kgsl_3d0_reg_memory";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+ clock-names = "core",
+ "iface",
+ "mem_iface";
+ clocks = <&mmcc OXILI_GFX3D_CLK>,
+ <&mmcc OXILICX_AHB_CLK>,
+ <&mmcc OXILICX_AXI_CLK>;
+ sram = <&gmu_sram>;
+ power-domains = <&mmcc OXILICX_GDSC>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
+ <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
+ interconnect-names = "gfx-mem",
+ "ocmem";
+
+ // iommus = <&gpu_iommu 0>;
+ };
+
mdss: mdss@...00000 {
status = "disabled";
base-commit: 226871e2eda4832d94c3239add7e52ad17b81ce5
--
2.30.0
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