linux-kernel - Re: [PATCH v7 02/28] coresight: etm4x: Skip accessing TRCPDCR in save/restore

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Message-ID: <20210125183957.GA894394@xps15>
Date:   Mon, 25 Jan 2021 11:39:57 -0700
From:   Mathieu Poirier <mathieu.poirier@...aro.org>
To:     Suzuki K Poulose <suzuki.poulose@....com>
Cc:     linux-arm-kernel@...ts.infradead.org, coresight@...ts.linaro.org,
        anshuman.khandual@....com, mike.leach@...aro.org,
        leo.yan@...aro.org, linux-kernel@...r.kernel.org,
        jonathan.zhouwen@...wei.com, catalin.marinas@....com,
        Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>,
        Tingwei Zhang <tingwei@...eaurora.org>
Subject: Re: [PATCH v7 02/28] coresight: etm4x: Skip accessing TRCPDCR in
 save/restore

On Sun, Jan 10, 2021 at 10:48:24PM +0000, Suzuki K Poulose wrote:
> When the ETM is affected by Qualcomm errata, modifying the
> TRCPDCR could cause the system hang. Even though this is
> taken care of during enable/disable ETM, the ETM state
> save/restore could still access the TRCPDCR. Make sure
> we skip the access during the save/restore.
> 
> Found by code inspection.
> 
> Fixes: 02510a5aa78df45 ("coresight: etm4x: Add support to skip trace unit power up")

The SHA1 should be 12 character long, something I commented on in V4.  I fixed
it.

> Cc: Mathieu Poirier <mathieu.poirier@...aro.org>
> Cc: Mike Leach <mike.leach@...aro.org>
> Cc: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
> Cc: Tingwei Zhang <tingwei@...eaurora.org>
> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@....com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 12 +++++++-----
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 76526679b998..cce65fc0c9aa 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -1373,7 +1373,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
>  
>  	state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR);
>  
> -	state->trcpdcr = readl(drvdata->base + TRCPDCR);
> +	if (!drvdata->skip_power_up)
> +		state->trcpdcr = readl(drvdata->base + TRCPDCR);
>  
>  	/* wait for TRCSTATR.IDLE to go up */
>  	if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
> @@ -1391,9 +1392,9 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
>  	 * potentially save power on systems that respect the TRCPDCR_PU
>  	 * despite requesting software to save/restore state.
>  	 */
> -	writel_relaxed((state->trcpdcr & ~TRCPDCR_PU),
> -			drvdata->base + TRCPDCR);
> -
> +	if (!drvdata->skip_power_up)
> +		writel_relaxed((state->trcpdcr & ~TRCPDCR_PU),
> +				drvdata->base + TRCPDCR);
>  out:
>  	CS_LOCK(drvdata->base);
>  	return ret;
> @@ -1488,7 +1489,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
>  
>  	writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
>  
> -	writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR);
> +	if (!drvdata->skip_power_up)
> +		writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR);
>  
>  	drvdata->state_needs_restore = false;
>  
> -- 
> 2.24.1
>