linux-kernel - [PATCH 4.19 17/58] clk: tegra30: Add hda clock default rates to clock driver

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Message-Id: <20210125183157.429028279@linuxfoundation.org>
Date:   Mon, 25 Jan 2021 19:39:18 +0100
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Jon Hunter <jonathanh@...dia.com>,
        Ion Agorria <ion@...rria.com>,
        Sameer Pujar <spujar@...dia.com>,
        Thierry Reding <treding@...dia.com>,
        Peter Geis <pgwipeout@...il.com>, Takashi Iwai <tiwai@...e.de>,
        Sasha Levin <sashal@...nel.org>
Subject: [PATCH 4.19 17/58] clk: tegra30: Add hda clock default rates to clock driver

From: Peter Geis <pgwipeout@...il.com>

[ Upstream commit f4eccc7fea203cfb35205891eced1ab51836f362 ]

Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.

This matches upstream t124 and downstream t30.

Acked-by: Jon Hunter <jonathanh@...dia.com>
Tested-by: Ion Agorria <ion@...rria.com>
Acked-by: Sameer Pujar <spujar@...dia.com>
Acked-by: Thierry Reding <treding@...dia.com>
Signed-off-by: Peter Geis <pgwipeout@...il.com>
Link: https://lore.kernel.org/r/20210108135913.2421585-2-pgwipeout@gmail.com
Signed-off-by: Takashi Iwai <tiwai@...e.de>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
 drivers/clk/tegra/clk-tegra30.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index e0aaecd98fbff..678019f86bc7a 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1274,6 +1274,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
 	{ TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
 	{ TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
+	{ TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
+	{ TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
 	/* must be the last entry */
 	{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
 };
-- 
2.27.0