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Message-ID: <0116e8c6-2e2a-173a-a903-e3d3e9f05a2c@redhat.com>
Date: Tue, 26 Jan 2021 19:16:42 +0100
From: Paolo Bonzini <pbonzini@...hat.com>
To: Chenyi Qiang <chenyi.qiang@...el.com>,
Sean Christopherson <sean.j.christopherson@...el.com>,
Vitaly Kuznetsov <vkuznets@...hat.com>,
Wanpeng Li <wanpengli@...cent.com>,
Jim Mattson <jmattson@...gle.com>,
Joerg Roedel <joro@...tes.org>,
Xiaoyao Li <xiaoyao.li@...el.com>
Cc: kvm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC 3/7] KVM: MMU: Rename the pkru to pkr
On 07/08/20 10:48, Chenyi Qiang wrote:
> PKRU represents the PKU register utilized in the protection key rights
> check for user pages. Protection Keys for Superviosr Pages (PKS) extends
> the protection key architecture to cover supervisor pages.
>
> Rename the *pkru* related variables and functions to *pkr* which stands
> for both of the PKRU and PKRS. It makes sense because both registers
> have the same format. PKS and PKU can also share the same bitmap to
> cache the conditions where protection key checks are needed.
>
> Signed-off-by: Chenyi Qiang <chenyi.qiang@...el.com>
> ---
> arch/x86/include/asm/kvm_host.h | 2 +-
> arch/x86/kvm/mmu.h | 12 ++++++------
> arch/x86/kvm/mmu/mmu.c | 18 +++++++++---------
> 3 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index be5363b21540..6b739d0d1c97 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -427,7 +427,7 @@ struct kvm_mmu {
> * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
> * Each domain has 2 bits which are ANDed with AD and WD from PKRU.
> */
> - u32 pkru_mask;
> + u32 pkr_mask;
>
> u64 *pae_root;
> u64 *lm_root;
> diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
> index 444bb9c54548..0c2fdf0abf22 100644
> --- a/arch/x86/kvm/mmu.h
> +++ b/arch/x86/kvm/mmu.h
> @@ -193,8 +193,8 @@ static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
> u32 errcode = PFERR_PRESENT_MASK;
>
> WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
> - if (unlikely(mmu->pkru_mask)) {
> - u32 pkru_bits, offset;
> + if (unlikely(mmu->pkr_mask)) {
> + u32 pkr_bits, offset;
>
> /*
> * PKRU defines 32 bits, there are 16 domains and 2
> @@ -202,15 +202,15 @@ static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
> * index of the protection domain, so pte_pkey * 2 is
> * is the index of the first bit for the domain.
> */
> - pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
> + pkr_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
>
> /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
> offset = (pfec & ~1) +
> ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
>
> - pkru_bits &= mmu->pkru_mask >> offset;
> - errcode |= -pkru_bits & PFERR_PK_MASK;
> - fault |= (pkru_bits != 0);
> + pkr_bits &= mmu->pkr_mask >> offset;
> + errcode |= -pkr_bits & PFERR_PK_MASK;
> + fault |= (pkr_bits != 0);
> }
>
> return -(u32)fault & errcode;
> diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
> index 6d6a0ae7800c..481442f5e27a 100644
> --- a/arch/x86/kvm/mmu/mmu.c
> +++ b/arch/x86/kvm/mmu/mmu.c
> @@ -4716,20 +4716,20 @@ static void update_permission_bitmask(struct kvm_vcpu *vcpu,
> * away both AD and WD. For all reads or if the last condition holds, WD
> * only will be masked away.
> */
> -static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
> +static void update_pkr_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
> bool ept)
> {
> unsigned bit;
> bool wp;
>
> if (ept) {
> - mmu->pkru_mask = 0;
> + mmu->pkr_mask = 0;
> return;
> }
>
> /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
> if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
> - mmu->pkru_mask = 0;
> + mmu->pkr_mask = 0;
> return;
> }
>
> @@ -4763,7 +4763,7 @@ static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
> /* PKRU.WD stops write access. */
> pkey_bits |= (!!check_write) << 1;
>
> - mmu->pkru_mask |= (pkey_bits & 3) << pfec;
> + mmu->pkr_mask |= (pkey_bits & 3) << pfec;
> }
> }
>
> @@ -4785,7 +4785,7 @@ static void paging64_init_context_common(struct kvm_vcpu *vcpu,
>
> reset_rsvds_bits_mask(vcpu, context);
> update_permission_bitmask(vcpu, context, false);
> - update_pkru_bitmask(vcpu, context, false);
> + update_pkr_bitmask(vcpu, context, false);
> update_last_nonleaf_level(vcpu, context);
>
> MMU_WARN_ON(!is_pae(vcpu));
> @@ -4815,7 +4815,7 @@ static void paging32_init_context(struct kvm_vcpu *vcpu,
>
> reset_rsvds_bits_mask(vcpu, context);
> update_permission_bitmask(vcpu, context, false);
> - update_pkru_bitmask(vcpu, context, false);
> + update_pkr_bitmask(vcpu, context, false);
> update_last_nonleaf_level(vcpu, context);
>
> context->page_fault = paging32_page_fault;
> @@ -4925,7 +4925,7 @@ static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
> }
>
> update_permission_bitmask(vcpu, context, false);
> - update_pkru_bitmask(vcpu, context, false);
> + update_pkr_bitmask(vcpu, context, false);
> update_last_nonleaf_level(vcpu, context);
> reset_tdp_shadow_zero_bits_mask(vcpu, context);
> }
> @@ -5032,7 +5032,7 @@ void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
> context->mmu_role.as_u64 = new_role.as_u64;
>
> update_permission_bitmask(vcpu, context, true);
> - update_pkru_bitmask(vcpu, context, true);
> + update_pkr_bitmask(vcpu, context, true);
> update_last_nonleaf_level(vcpu, context);
> reset_rsvds_bits_mask_ept(vcpu, context, execonly);
> reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
> @@ -5103,7 +5103,7 @@ static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
> }
>
> update_permission_bitmask(vcpu, g_context, false);
> - update_pkru_bitmask(vcpu, g_context, false);
> + update_pkr_bitmask(vcpu, g_context, false);
> update_last_nonleaf_level(vcpu, g_context);
> }
>
>
Reviewed-by: Paolo Bonzini <pbonzini@...hat.com>
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