[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAL_JsqKuvD1s0u5uphmc3o4d7vsNui6hC2b9Q3woE-nshfJi0g@mail.gmail.com>
Date: Wed, 27 Jan 2021 11:39:19 -0600
From: Rob Herring <robh@...nel.org>
To: Shradha Todi <shradha.t@...sung.com>
Cc: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
PCI <linux-pci@...r.kernel.org>,
Jingoo Han <jingoohan1@...il.com>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Pankaj Dubey <pankaj.dubey@...sung.com>,
sriram.dash@...sung.com, niyas.ahmed@...sung.com,
p.rajanbabu@...sung.com, l.mehra@...sung.com, hari.tv@...sung.com
Subject: Re: [PATCH v2] PCI: dwc: Add upper limit address for outbound iATU
On Wed, Jan 6, 2021 at 4:52 AM Shradha Todi <shradha.t@...sung.com> wrote:
>
> The size parameter is unsigned long type which can accept size > 4GB. In
> that case, the upper limit address must be programmed. Add support to
> program the upper limit address and set INCREASE_REGION_SIZE in case size >
> 4GB.
>
> Signed-off-by: Shradha Todi <shradha.t@...sung.com>
> ---
> v1: https://lkml.org/lkml/2020/12/20/187
> v2:
> Addressed Rob's review comment and added PCI version check condition to
> avoid writing to reserved registers.
>
> drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 files changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Rob Herring <robh@...nel.org>
Powered by blists - more mailing lists