linux-kernel - [PATCH v1 2/3] arm64: dts: mt6779: add emi node

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Message-ID: <1611746924-12287-3-git-send-email-EastL.Lee@mediatek.com>
Date:   Wed, 27 Jan 2021 19:28:43 +0800
From:   EastL Lee <EastL.Lee@...iatek.com>
To:     Sean Wang <sean.wang@...iatek.com>
CC:     <vkoul@...nel.org>, <robh+dt@...nel.org>, <mark.rutland@....com>,
        <matthias.bgg@...il.com>, <dmaengine@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        <wsd_upstream@...iatek.com>, <cc.hwang@...iatek.com>,
        <joane.wang@...iatek.com>, <adrian-cj.hung@...iatek.com>,
        EastL Lee <EastL.Lee@...iatek.com>
Subject: [PATCH v1 2/3] arm64: dts: mt6779: add emi node

add emicen & emichn & emimpu node

Signed-off-by: EastL Lee <EastL.Lee@...iatek.com>
---
 arch/arm64/boot/dts/mediatek/mt6779.dtsi | 34 ++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 370f309..bb34537 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -267,5 +267,39 @@
 			#clock-cells = <1>;
 		};
 
+		emichn: emichn@...35000 {
+			compatible = "mediatek,mt6779-emichn",
+				"mediatek,common-emichn";
+			reg = <0 0x10235000 0 0x1000>,
+				<0 0x10245000 0 0x1000>;
+		};
+
+		emicen: emicen@...19000 {
+			compatible = "mediatek,mt6779-emicen",
+				"mediatek,common-emicen";
+			reg = <0 0x10219000 0 0x1000>;
+			mediatek,emi-reg = <&emichn>;
+		};
+
+		emimpu:emimpu@...26000 {
+			compatible = "mediatek,mt6779-emimpu",
+				"mediatek,common-emimpu";
+			reg = <0 0x10226000 0 0x1000>;
+			mediatek,emi-reg = <&emicen>;
+			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
+			region_cnt = <32>;
+			domain_cnt = <16>;
+			addr_align = <16>;
+			ap_region = <31>;
+			ap_apc = <0 5 5 5 0 0 6 5>,
+				<0 0 5 0 0 1 5 5>;
+			dump = <0x1f0 0x1f8 0x1fc>;
+			clear = <0x160 0xffffffff 16>,
+				<0x200 0x00000003 16>,
+				<0x1f0 0x80000000 1>;
+			clear_md = <0x1fc 0x80000000 1>;
+			ctrl_intf = <1>;
+			slverr = <0>;
+		};
 	};
 };
-- 
1.9.1