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Message-ID: <1611794619.1947.0.camel@mhfsdcap03>
Date:   Thu, 28 Jan 2021 08:43:39 +0800
From:   Yongqiang Niu <yongqiang.niu@...iatek.com>
To:     Chun-Kuang Hu <chunkuang.hu@...nel.org>
CC:     CK Hu <ck.hu@...iatek.com>, Philipp Zabel <p.zabel@...gutronix.de>,
        "Rob Herring" <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Mark Rutland <mark.rutland@....com>,
        DTML <devicetree@...r.kernel.org>,
        David Airlie <airlied@...ux.ie>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        DRI Development <dri-devel@...ts.freedesktop.org>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@...ts.infradead.org>,
        "Daniel Vetter" <daniel@...ll.ch>,
        Hsin-Yi Wang <hsinyi@...omium.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v3, 07/15] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for
 multi-layer usecase

On Tue, 2021-01-12 at 07:59 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu <yongqiang.niu@...iatek.com> 於 2021年1月11日 週一 下午3:44寫道:
> >
> > enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
> 
> Could you describe more information? Without this patch, what would happen?
> 

without this patch, ovl will hang up when more than 1 layer enabled

> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@...iatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index b47c238..4934bee 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -23,6 +23,7 @@
> >  #define DISP_REG_OVL_RST                       0x0014
> >  #define DISP_REG_OVL_ROI_SIZE                  0x0020
> >  #define DISP_REG_OVL_DATAPATH_CON              0x0024
> > +#define OVL_LAYER_SMI_ID_EN                            BIT(0)
> >  #define OVL_BGCLR_SEL_IN                               BIT(2)
> >  #define DISP_REG_OVL_ROI_BGCLR                 0x0028
> >  #define DISP_REG_OVL_SRC_CON                   0x002c
> > @@ -61,6 +62,7 @@ struct mtk_disp_ovl_data {
> >         unsigned int gmc_bits;
> >         unsigned int layer_nr;
> >         bool fmt_rgb565_is_0;
> > +       bool smi_id_en;
> >  };
> >
> >  /**
> > @@ -116,7 +118,17 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
> >
> >  static void mtk_ovl_start(struct mtk_ddp_comp *comp)
> >  {
> > +       struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
> > +
> >         writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
> > +
> > +       if(ovl->data->smi_id_en) {
> > +               unsigned int reg;
> > +
> > +               reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> > +               reg = reg | OVL_LAYER_SMI_ID_EN;
> > +               writel_relaxed(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> 
> I think this setting should before write 1 to DISP_REG_OVL_EN.
> 
> > +       }
> >  }
> >
> >  static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
> 
> Should clear DISP_REG_OVL_DATAPATH_CON when stop?
> 
> Regards,
> Chun-Kuang.
> 
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@...ts.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

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