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Message-Id: <20210129190038.1001626-2-atish.patra@wdc.com>
Date: Fri, 29 Jan 2021 11:00:37 -0800
From: Atish Patra <atish.patra@....com>
To: linux-kernel@...r.kernel.org
Cc: Sebastien Van Cauwenberghe <svancau@...il.com>,
Atish Patra <atish.patra@....com>,
Albert Ou <aou@...s.berkeley.edu>,
Anup Patel <anup.patel@....com>,
Ard Biesheuvel <ardb@...nel.org>,
"Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
linux-riscv@...ts.infradead.org,
Nick Desaulniers <ndesaulniers@...ogle.com>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Zong Li <zong.li@...ive.com>
Subject: [PATCH 2/3] riscv: Align on L1_CACHE_BYTES when STRICT_KERNEL_RWX
From: Sebastien Van Cauwenberghe <svancau@...il.com>
Allows the sections to be aligned on smaller boundaries and
therefore results in a smaller kernel image size.
Signed-off-by: Sebastien Van Cauwenberghe <svancau@...il.com>
Reviewed-by: Atish Patra <atish.patra@....com>
---
arch/riscv/include/asm/set_memory.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/set_memory.h b/arch/riscv/include/asm/set_memory.h
index 211eb8244a45..8b80c80c7f1a 100644
--- a/arch/riscv/include/asm/set_memory.h
+++ b/arch/riscv/include/asm/set_memory.h
@@ -32,14 +32,14 @@ bool kernel_page_present(struct page *page);
#endif /* __ASSEMBLY__ */
-#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
+#ifdef CONFIG_STRICT_KERNEL_RWX
#ifdef CONFIG_64BIT
#define SECTION_ALIGN (1 << 21)
#else
#define SECTION_ALIGN (1 << 22)
#endif
-#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
+#else /* !CONFIG_STRICT_KERNEL_RWX */
#define SECTION_ALIGN L1_CACHE_BYTES
-#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
+#endif /* CONFIG_STRICT_KERNEL_RWX */
#endif /* _ASM_RISCV_SET_MEMORY_H */
--
2.25.1
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