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Message-ID: <54655f17-2e4a-cc1e-262c-b365e3de9b20@google.com>
Date: Sat, 30 Jan 2021 15:51:39 -0800 (PST)
From: David Rientjes <rientjes@...gle.com>
To: Ben Widawsky <ben.widawsky@...el.com>
cc: linux-cxl@...r.kernel.org, Dan Williams <dan.j.williams@...el.com>,
Jonathan Corbet <corbet@....net>, linux-acpi@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-nvdimm@...ts.01.org,
linux-pci@...r.kernel.org, Bjorn Helgaas <helgaas@...nel.org>,
Chris Browy <cbrowy@...ry-design.com>,
Christoph Hellwig <hch@...radead.org>,
Ira Weiny <ira.weiny@...el.com>,
Jon Masters <jcm@...masters.org>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>,
Rafael Wysocki <rafael.j.wysocki@...el.com>,
Randy Dunlap <rdunlap@...radead.org>,
Vishal Verma <vishal.l.verma@...el.com>,
daniel.lll@...baba-inc.com,
"John Groves (jgroves)" <jgroves@...ron.com>,
"Kelley, Sean V" <sean.v.kelley@...el.com>
Subject: Re: [PATCH 01/14] cxl/mem: Introduce a driver for CXL-2.0-Type-3
endpoints
On Fri, 29 Jan 2021, Ben Widawsky wrote:
> diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> new file mode 100644
> index 000000000000..3b66b46af8a0
> --- /dev/null
> +++ b/drivers/cxl/Kconfig
> @@ -0,0 +1,35 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +menuconfig CXL_BUS
> + tristate "CXL (Compute Express Link) Devices Support"
> + depends on PCI
> + help
> + CXL is a bus that is electrically compatible with PCI Express, but
> + layers three protocols on that signalling (CXL.io, CXL.cache, and
> + CXL.mem). The CXL.cache protocol allows devices to hold cachelines
> + locally, the CXL.mem protocol allows devices to be fully coherent
> + memory targets, the CXL.io protocol is equivalent to PCI Express.
> + Say 'y' to enable support for the configuration and management of
> + devices supporting these protocols.
> +
> +if CXL_BUS
> +
> +config CXL_MEM
> + tristate "CXL.mem: Endpoint Support"
Nit: "CXL.mem: Memory Devices" or "CXL Memory Devices: CXL.mem" might look
better, but feel free to ignore.
Acked-by: David Rientjes <rientjes@...gle.com>
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