linux-kernel - Re: [PATCH 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192

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Message-ID: <03eed306-c9f3-96ed-208d-24a2017b2d3d@gmail.com>
Date:   Sun, 31 Jan 2021 14:29:43 +0100
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Weiyi Lu <weiyi.lu@...iatek.com>, Rob Herring <robh@...nel.org>,
        Nicolas Boichat <drinkcat@...omium.org>
Cc:     devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org,
        linux-clk@...r.kernel.org, srv_heupstream@...iatek.com,
        Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH 2/2] arm64: dts: mediatek: Correct UART0 bus clock of
 MT8192



On 22/12/2020 14:40, Weiyi Lu wrote:
> infra_uart0 clock is the real one what uart0 uses as bus clock.
> 
> Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 92dcfbd..ac5dca6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -283,7 +283,7 @@
>  				     "mediatek,mt6577-uart";
>  			reg = <0 0x11002000 0 0x1000>;
>  			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>, <&clk26m>;
> +			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;

Please update the clocks for all nodes to use the clock driver, not just uart or
uart0.

Thanks,
Matthias

>  			clock-names = "baud", "bus";
>  			status = "disabled";
>  		};
>