linux-kernel - RE: [PATCH 1/4] drivers: phy: add support for Armada CP110 UTMI PHY

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Message-ID: <DM5PR18MB1452B34AC0C36693C6CE294DCAB79@DM5PR18MB1452.namprd18.prod.outlook.com>
Date:   Sun, 31 Jan 2021 13:34:46 +0000
From:   Kostya Porotchkin <kostap@...vell.com>
To:     Lubomir Rintel <lkundrak@...sk>
CC:     "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "mw@...ihalf.com" <mw@...ihalf.com>,
        "andrew@...n.ch" <andrew@...n.ch>,
        "jaz@...ihalf.com" <jaz@...ihalf.com>,
        "gregory.clement@...tlin.com" <gregory.clement@...tlin.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        Nadav Haklai <nadavh@...vell.com>,
        "vkoul@...nel.org" <vkoul@...nel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>,
        Stefan Chulski <stefanc@...vell.com>,
        "kishon@...com" <kishon@...com>, Ben Peled <bpeled@...vell.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "sebastian.hesselbarth@...il.com" <sebastian.hesselbarth@...il.com>
Subject: RE: [PATCH 1/4] drivers: phy: add support for Armada CP110 UTMI PHY

Hello, Lubomir,

Thank you for your review!

> > +static void mvebu_cp110_utmi_port_setup(struct mvebu_cp110_utmi_port
> > +*port) {
> > +	u32 reg;
> > +
> > +	/*
> > +	 * Setup PLL. 40MHz clock used to be the default, being 25MHz now.
> > +	 * See the functional specification for details.
> 
> I tried to, couldn't find it. Perhaps you could elaborate more here, or include a
> link in the header.
[KP] This is the frequency of a quartz resonator connected to REFCLK_XIN/REFCLK_XOUT SoC pins.
The default crystal frequency used now at all Marvell reference platforms is 25MHz.
The default out of reset state register values are however have settings for 40MHz crystal used at the time of RTL code freeze.
I will mention this fact in the second patch version.

> 
> > +	/* PLL Power down if all UTMI PHYs are down */
> > +	regmap_clear_bits(utmi->syscon, SYSCON_USB_CFG_REG,
> > +USB_CFG_PLL_MASK);
> > +
> > +	return 0;
> > +}
> > +
> > +static int mvebu_cp110_utmi_phy_power_on(struct phy *phy) {
> > +	struct mvebu_cp110_utmi_port *port = phy_get_drvdata(phy);
> > +	struct mvebu_cp110_utmi *utmi = port->priv;
> > +	struct device *dev = &phy->dev;
> > +	int ret;
> > +	u32 reg;
> > +
> > +	/* It is necessary to power off UTMI before configuration */
> > +	ret = mvebu_cp110_utmi_phy_power_off(phy);
> 
> mvebu_cp110_utmi_phy_power_off() also sometimes, but not always, shuts
> down the PLL. Is that necessary? I guess all you care about is the bit in
> UTMI_PHY_CFG_PU_MASK?
[KP] Not sure I fully understand the question. Both UTMI PHYs are using the same dedicated PLL source.
I am trying to save the power to shutting down this PLL when both PHY ports are down.

> 
> > +
> > +		ret = of_property_read_u32(child, "reg", &val);
> > +		if (ret < 0) {
> > +			dev_err(dev, "missing 'reg' property (%d)\n", ret);
> 
> A nit: the property is not necessarily missing -- it could be malformed (with ret
> of -ENODATA or -EOVERFLOW).
> 
> Also, perhaps you want to log the name of node that has problems ("%pOF",
> child); also in the error messages below.
[KP] OK, will do it in the second patch version. 

> 
> > +			continue;
> > +		}
> > +
> > +		if (val >= UTMI_PHY_PORTS) {
> > +			dev_err(dev, "invalid 'reg' property\n");
> > +			continue;
> > +		}
> 
> Perhaps you could just squelch those two warnings together:
> 
> 
> 	if (ret || val >= UTMI_PHY_PORTS) {
> 		dev_err(dev, "invalid 'reg' property on %pOF\n", child);
> 		continue;
> 	}
> 
[KP] Yes, it will definitely be better, thank you.

> > --
> > 2.17.1
> >
> 
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