linux-kernel - Re: [PATCH 1/3] MIPS: kernel: Support extracting off-line stack traces from user-space with perf

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <7c081c6f-bf47-353d-95c0-52e8640dc938@loongson.cn>
Date:   Mon, 1 Feb 2021 20:56:06 +0800
From:   Tiezhu Yang <yangtiezhu@...ngson.cn>
To:     Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>, linux-mips@...r.kernel.org,
        linux-kernel@...r.kernel.org, Xuefeng Li <lixuefeng@...ngson.cn>,
        David Daney <david.daney@...ium.com>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Archer Yan <ayan@...ecomp.com>
Subject: Re: [PATCH 1/3] MIPS: kernel: Support extracting off-line stack
 traces from user-space with perf

On 02/01/2021 06:43 PM, Thomas Bogendoerfer wrote:
> On Tue, Dec 29, 2020 at 08:55:59PM +0800, Tiezhu Yang wrote:
>> +++ b/arch/mips/include/uapi/asm/perf_regs.h
>> @@ -0,0 +1,42 @@
>> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
>> +#ifndef _ASM_MIPS_PERF_REGS_H
>> +#define _ASM_MIPS_PERF_REGS_H
>> +
>> +enum perf_event_mips_regs {
>> +	PERF_REG_MIPS_PC,
>> +	PERF_REG_MIPS_R1,
>> +	PERF_REG_MIPS_R2,
>> +	PERF_REG_MIPS_R3,
>> +	PERF_REG_MIPS_R4,
>> +	PERF_REG_MIPS_R5,
>> +	PERF_REG_MIPS_R6,
>> +	PERF_REG_MIPS_R7,
>> +	PERF_REG_MIPS_R8,
>> +	PERF_REG_MIPS_R9,
>> +	PERF_REG_MIPS_R10,
>> +	PERF_REG_MIPS_R11,
>> +	PERF_REG_MIPS_R12,
>> +	PERF_REG_MIPS_R13,
>> +	PERF_REG_MIPS_R14,
>> +	PERF_REG_MIPS_R15,
>> +	PERF_REG_MIPS_R16,
>> +	PERF_REG_MIPS_R17,
>> +	PERF_REG_MIPS_R18,
>> +	PERF_REG_MIPS_R19,
>> +	PERF_REG_MIPS_R20,
>> +	PERF_REG_MIPS_R21,
>> +	PERF_REG_MIPS_R22,
>> +	PERF_REG_MIPS_R23,
>> +	PERF_REG_MIPS_R24,
>> +	PERF_REG_MIPS_R25,
>> +	/*
>> +	 * 26 and 27 are k0 and k1, they are always clobbered thus not
>> +	 * stored.
>> +	 */
> haveing this hole here make all code more complicated. Does it hurt
> to have R26 and R27 in the list ?

I think there is no effect if have R26 and R27 in the list.

In the perf_reg_value(), PERF_REG_MIPS_R{26,27} are default case.

+u64 perf_reg_value(struct pt_regs *regs, int idx)
+{
+ long v;
+
+ switch (idx) {
+ case PERF_REG_MIPS_PC:
+ v = regs->cp0_epc;
+ break;
+ case PERF_REG_MIPS_R1 ... PERF_REG_MIPS_R25:
+ v = regs->regs[idx - PERF_REG_MIPS_R1 + 1];
+ break;
+ case PERF_REG_MIPS_R28 ... PERF_REG_MIPS_R31:
+ v = regs->regs[idx - PERF_REG_MIPS_R28 + 28];
+ break;
+
+ default:
+ WARN_ON_ONCE(1);
+ return 0;
+ }
+
+ return (s64)v; /* Sign extend if 32-bit. */
+} Should I modify enum perf_event_mips_regs to add R26 and R27,
and then send v2?

Thanks,
Tiezhu

>
> Thomas.
>