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Message-ID: <fd65e539-d8cf-e1d0-103b-ad8154a42173@huawei.com>
Date:   Mon, 1 Feb 2021 14:22:38 +0000
From:   John Garry <john.garry@...wei.com>
To:     Shunsuke Nakamura <nakamura.shun@...fujitsu.com>,
        <will@...nel.org>, <mathieu.poirier@...aro.org>,
        <leo.yan@...aro.org>, <peterz@...radead.org>, <mingo@...hat.com>,
        <acme@...nel.org>, <mark.rutland@....com>,
        <alexander.shishkin@...ux.intel.com>, <jolsa@...hat.com>,
        <namhyung@...nel.org>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <nakamura.shun@...itsu.com>
Subject: Re: [PATCH v4 2/4] perf vendor events: Add L2I_TLB, SVE, SIMD, and FP
 events

On 01/02/2021 11:13, Shunsuke Nakamura wrote:

I think that you will need to fix the subject, like:

perf vendor events arm64: Add more common and uarch events

> Add the following events.

It would be good to mention your reference document.

> 
> Common architectural events:
>    - L2I_TLB_REFILL
>    - L2I_TLB
>    - SIMD_INST_RETIRED
>    - SVE_INST_RETIRED
> 
> Common microarchitectural events:
>    - UOP_SPEC
>    - SVE_MATH_SPEC
>    - FP_SPEC
>    - FP_FMA_SPEC
>    - FP_RECPE_SPEC
>    - FP_CVT_SPEC
>    - ASE_SVE_INT_SPEC
>    - SVE_PRED_SPEC
>    - SVE_MOVPRFX_SPEC
>    - SVE_MOVPRFX_U_SPEC
>    - ASE_SVE_LD_SPEC
>    - ASE_SVE_ST_SPEC
>    - PRF_SPEC
>    - BASE_LD_REG_SPEC
>    - BASE_ST_REG_SPEC
>    - SVE_LDR_REG_SPEC
>    - SVE_STR_REG_SPEC
>    - SVE_LDR_PREG_SPEC
>    - SVE_STR_PREG_SPEC
>    - SVE_PRF_CONTIG_SPEC
>    - ASE_SVE_LD_MULTI_SPEC
>    - ASE_SVE_ST_MULTI_SPEC
>    - SVE_LD_GATHER_SPEC
>    - SVE_ST_SCATTER_SPEC
>    - SVE_PRF_GATHER_SPEC
>    - SVE_LDFF_SPEC
>    - FP_SCALE_OPS_SPEC
>    - FP_FIXED_OPS_SPEC
>    - FP_HP_SCALE_OPS_SPEC
>    - FP_HP_FIXED_OPS_SPEC
>    - FP_SP_SCALE_OPS_SPEC
>    - FP_SP_FIXED_OPS_SPEC
>    - FP_DP_SCALE_OPS_SPEC
>    - FP_DP_FIXED_OPS_SPEC
> 
> Signed-off-by: Shunsuke Nakamura<nakamura.shun@...itsu.com>

Apart from those, above:

Reviewed-by: John Garry <john.garry@...wei.com>

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