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Message-Id: <83e49b6e-9c9d-407e-8ac1-f3fad63df915@www.fastmail.com> Date: Mon, 01 Feb 2021 12:03:02 +0800 From: "Jiaxun Yang" <jiaxun.yang@...goat.com> To: "Jinyang He" <hejinyang@...ngson.cn>, "Thomas Bogendoerfer" <tsbogend@...ha.franken.de>, "Steven Rostedt" <rostedt@...dmis.org>, "Ingo Molnar" <mingo@...hat.com> Cc: "Wu Zhangjin" <wuzhangjin@...il.com>, "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>, linux-kernel@...r.kernel.org, "Huacai Chen" <chenhuacai@...nel.org>, "Tiezhu Yang" <yangtiezhu@...ngson.cn> Subject: Re: [PATCH 1/3] MIPS: ftrace: Fix N32 save registers On Mon, Feb 1, 2021, at 9:12 AM, Jinyang He wrote: > On 01/31/2021 06:38 PM, Jiaxun Yang wrote: > > > > > On Sun, Jan 31, 2021, at 4:14 PM, Jinyang He wrote: > >> CONFIG_64BIT is confusing. N32 also pass parameters by a0~a7. > > Do we have NEW kernel build? > > CONFIG_64BIT assumed N64 as kernel ABI. > > > > > > -Jiaxun > Hi, Jiaxun, > > Thank you for your reply, and now I know. Before that, I saw the macro > from arch/mips/include/asm/regdef.h and thought it needed to be modified > here. But that seems have no sence. > Please ignore this patch. I guess that's for uapi consideration. Thanks. - Jiaxun > > Thanks, > Jinyang > > >> Signed-off-by: Jinyang He <hejinyang@...ngson.cn> > >> --- > >> arch/mips/kernel/mcount.S | 4 ++-- > >> 1 file changed, 2 insertions(+), 2 deletions(-) > >> > >> diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S > >> index cff52b2..808257a 100644 > >> --- a/arch/mips/kernel/mcount.S > >> +++ b/arch/mips/kernel/mcount.S > >> @@ -27,7 +27,7 @@ > >> PTR_S a1, PT_R5(sp) > >> PTR_S a2, PT_R6(sp) > >> PTR_S a3, PT_R7(sp) > >> -#ifdef CONFIG_64BIT > >> +#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 > >> PTR_S a4, PT_R8(sp) > >> PTR_S a5, PT_R9(sp) > >> PTR_S a6, PT_R10(sp) > >> @@ -42,7 +42,7 @@ > >> PTR_L a1, PT_R5(sp) > >> PTR_L a2, PT_R6(sp) > >> PTR_L a3, PT_R7(sp) > >> -#ifdef CONFIG_64BIT > >> +#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 > >> PTR_L a4, PT_R8(sp) > >> PTR_L a5, PT_R9(sp) > >> PTR_L a6, PT_R10(sp) > >> -- > >> 2.1.0 > >> > >> > > -- - Jiaxun
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