linux-kernel - Re: [PATCH v3] clk: exynos7: Keep aclk_fsys1

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Message-ID: <2562d6ab-f7ec-8445-7207-a83318dd6402@samsung.com>
Date:   Mon, 1 Feb 2021 13:50:50 +0900
From:   Chanwoo Choi <cw00.choi@...sung.com>
To:     Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>,
        kgene@...nel.org, krzk@...nel.org, mturquette@...libre.com,
        sboyd@...nel.org
Cc:     s.nawrocki@...sung.com, tomasz.figa@...il.com,
        linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3] clk: exynos7: Keep aclk_fsys1_200 enabled

On 2/1/21 2:04 AM, Paweł Chmiel wrote:
> This clock must be always enabled to allow access to any registers in
> fsys1 CMU. Until proper solution based on runtime PM is applied
> (similar to what was done for Exynos5433), fix this by calling
> clk_prepare_enable() directly from clock provider driver.
> 
> It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
> UFS module is probed before pmic used to power that device.
> In this case defer probe was happening and that clock was disabled by
> UFS driver, causing whole boot to hang on next CMU access.
> 
> Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>
> ---
> Changes from v2:
>   - Avoid __clk_lookup() call when enabling clock
> Changes from v1:
>   - Instead of marking clock as critical, enable it manually in driver.
> ---
>  drivers/clk/samsung/clk-exynos7.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index c1ff715e960c..24d3fc5c5d0f 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -6,6 +6,7 @@
>  
>  #include <linux/clk-provider.h>
>  #include <linux/of.h>
> +#include <linux/clk.h>
>  
>  #include "clk.h"
>  #include <dt-bindings/clock/exynos7-clk.h>
> @@ -570,7 +571,18 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
>  
>  static void __init exynos7_clk_top1_init(struct device_node *np)
>  {
> -	samsung_cmu_register_one(np, &top1_cmu_info);
> +	struct samsung_clk_provider *ctx;
> +	struct clk_hw **hws;
> +
> +	ctx = samsung_cmu_register_one(np, &top1_cmu_info);
> +	if (!ctx)
> +		return;
> +	hws = ctx->clk_data.hws;
> +
> +	/*
> +	 * Keep top FSYS1 aclk enabled permanently. It's required for CMU register access.
> +	 */
> +	clk_prepare_enable(hws[CLK_ACLK_FSYS1_200]->clk);
>  }
>  
>  CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
> 

Acked-by: Chanwoo Choi <cw00.choi@...sung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics