linux-kernel - Re: [PATCH v7 4/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller

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Date:   Tue, 2 Feb 2021 16:54:25 +0100
From:   Arnd Bergmann <arnd@...nel.org>
To:     "Leizhen (ThunderTown)" <thunder.leizhen@...wei.com>
Cc:     Russell King <rmk+kernel@....linux.org.uk>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Will Deacon <will.deacon@....com>,
        Haojian Zhuang <haojian.zhuang@...il.com>,
        Arnd Bergmann <arnd@...db.de>,
        Rob Herring <robh+dt@...nel.org>,
        Wei Xu <xuwei5@...ilicon.com>,
        devicetree <devicetree@...r.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v7 4/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller

On Tue, Feb 2, 2021 at 1:18 PM Leizhen (ThunderTown)
<thunder.leizhen@...wei.com> wrote:
> On 2021/2/2 16:44, Arnd Bergmann wrote:
> >
> > To have a more useful performance number, try mentioning the
> > most performance sensitive non-coherent DMA master on one
> > of the chips that has this cache controller, and a high-level
> > performance number such as "1.2% more network packets per
> > second" if that is something you can measure easily.
>
> It's not easy. My board only have debugging NIC, only the downstream
> products have high-speed service NIC. Software needs to be packaged
> layer by layer.
>
> >
> > Of course, if all high-speed DMA masters on this chip are
> > cache coherent, there is no need for performance numbers, just
> > mention that we don't care about speed in that case.
>
> It's not cache coherent, otherwise, the L3 cache does not need to be
> operated.

Ok, I see. In this case, just explain that the high-speed NIC is not
cache-coherent, so this is expected to make a difference, even if you
can't quantify it exactly.

       Arnd