linux-kernel - Re: [PATCH] mtd: rawnand: Do not check for bad block if bbt is unavailable

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Message-ID: <F55F9D7B-0542-448E-A711-D1035E467ACA@linaro.org>
Date:   Wed, 03 Feb 2021 17:11:31 +0530
From:   Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To:     Boris Brezillon <boris.brezillon@...labora.com>, richard@....at
CC:     Miquel Raynal <miquel.raynal@...tlin.com>, vigneshr@...com,
        linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, bjorn.andersson@...aro.org
Subject: Re: [PATCH] mtd: rawnand: Do not check for bad block if bbt is unavailable



On 3 February 2021 4:54:22 PM IST, Boris Brezillon <boris.brezillon@...labora.com> wrote:
>On Wed, 03 Feb 2021 16:22:42 +0530
>Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org> wrote:
>
>> On 3 February 2021 3:49:14 PM IST, Boris Brezillon
><boris.brezillon@...labora.com> wrote:
>> >On Wed, 03 Feb 2021 15:42:02 +0530
>> >Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org> wrote:
>> >  
>> >> >> 
>> >> >> I got more information from the vendor, Telit. The access to
>the  
>> >3rd    
>> >> >partition is protected by Trustzone and any access in non
>privileged
>> >> >mode (where Linux kernel runs) causes kernel panic and the device
>> >> >reboots.   
>> >
>> >Out of curiosity, is it a per-CS-line thing or is this section
>> >protected on all CS?
>> >  
>> 
>> Sorry, I didn't get your question. 
>
>The qcom controller can handle several chips, each connected through a
>different CS (chip-select) line, right? I'm wondering if the firmware
>running in secure mode has the ability to block access for a specific
>CS line or if all CS lines have the same constraint. That will impact
>the way you describe it in your DT (in one case the secure-region
>property should be under the controller node, in the other case it
>should be under the NAND chip node).

Right. I believe the implementation is common to all NAND chips so the property should be in the controller node. 

Thanks, 
Mani

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