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Message-ID: <20210203133138.10754-4-kostap@marvell.com>
Date: Wed, 3 Feb 2021 15:31:30 +0200
From: <kostap@...vell.com>
To: <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
CC: <linux@...linux.org.uk>, <robh+dt@...nel.org>,
<sebastian.hesselbarth@...il.com>, <gregory.clement@...tlin.com>,
<andrew@...n.ch>, <mw@...ihalf.com>, <jaz@...ihalf.com>,
<nadavh@...vell.com>, <stefanc@...vell.com>, <bpeled@...vell.com>,
"Konstantin Porotchkin" <kostap@...vell.com>
Subject: [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce
From: Konstantin Porotchkin <kostap@...vell.com>
Add SDIO mode pin control configration for CP0 on A8K DB.
Signed-off-by: Konstantin Porotchkin <kostap@...vell.com>
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++++
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index 293403a1a333..179218774ba9 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -47,6 +47,12 @@
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
+ sdhci_pins: sdhi-pins {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61", "mpp62";
+ marvell,function = "sdio";
+ };
+
nand_pins: nand-pins {
marvell,pins =
"mpp15", "mpp16", "mpp17", "mpp18",
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index ee67c70bf02e..64100ae204da 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -70,6 +70,12 @@
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
+
+ sdhci_pins: sdhi-pins {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61", "mpp62";
+ marvell,function = "sdio";
+ };
};
};
--
2.17.1
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