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Date: Thu, 4 Feb 2021 20:00:13 +0100
From: Marcin Wojtas <mw@...ihalf.com>
To: Stefan Chulski <stefanc@...vell.com>
Cc: netdev <netdev@...r.kernel.org>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
"David S. Miller" <davem@...emloft.net>, nadavh@...vell.com,
Yan Markman <ymarkman@...vell.com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Jakub Kicinski <kuba@...nel.org>,
Russell King - ARM Linux <linux@...linux.org.uk>,
Andrew Lunn <andrew@...n.ch>,
Russell King <rmk+kernel@...linux.org.uk>, atenart@...nel.org
Subject: Re: [PATCH v7 net-next 13/15] net: mvpp2: add PPv23 RX FIFO flow control
Hi,
wt., 2 lut 2021 o 09:18 <stefanc@...vell.com> napisał(a):
>
> From: Stefan Chulski <stefanc@...vell.com>
>
> New FIFO flow control feature were added in PPv23.
s/were/was/
Thanks,
Marcin
> PPv2 FIFO polled by HW and trigger pause frame if FIFO
> fill level is below threshold.
> FIFO HW flow control enabled with CM3 RXQ&BM flow
> control with ethtool.
> Current FIFO thresholds is:
> 9KB for port with maximum speed 10Gb/s port
> 4KB for port with maximum speed 5Gb/s port
> 2KB for port with maximum speed 1Gb/s port
>
> Signed-off-by: Stefan Chulski <stefanc@...vell.com>
> ---
> drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 15 ++++++
> drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 53 ++++++++++++++++++++
> 2 files changed, 68 insertions(+)
>
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> index 1967493..9947385 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> @@ -770,6 +770,18 @@
> #define MVPP2_TX_FIFO_THRESHOLD(kb) \
> ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
>
> +/* RX FIFO threshold in 1KB granularity */
> +#define MVPP23_PORT0_FIFO_TRSH (9 * 1024)
> +#define MVPP23_PORT1_FIFO_TRSH (4 * 1024)
> +#define MVPP23_PORT2_FIFO_TRSH (2 * 1024)
> +
> +/* RX Flow Control Registers */
> +#define MVPP2_RX_FC_REG(port) (0x150 + 4 * (port))
> +#define MVPP2_RX_FC_EN BIT(24)
> +#define MVPP2_RX_FC_TRSH_OFFS 16
> +#define MVPP2_RX_FC_TRSH_MASK (0xFF << MVPP2_RX_FC_TRSH_OFFS)
> +#define MVPP2_RX_FC_TRSH_UNIT 256
> +
> /* MSS Flow control */
> #define MSS_SRAM_SIZE 0x800
> #define MSS_FC_COM_REG 0
> @@ -1502,6 +1514,8 @@ struct mvpp2_bm_pool {
>
> void mvpp2_dbgfs_cleanup(struct mvpp2 *priv);
>
> +void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en);
> +
> #ifdef CONFIG_MVPP2_PTP
> int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv);
> void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp,
> @@ -1534,4 +1548,5 @@ static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port)
> {
> return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;
> }
> +
> #endif
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> index f153060..06d3239 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> @@ -6537,6 +6537,8 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
> mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause);
> mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause);
> }
> + if (port->priv->hw_version == MVPP23)
> + mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause);
> }
>
> mvpp2_port_enable(port);
> @@ -7005,6 +7007,55 @@ static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
> mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
> }
>
> +/* Configure Rx FIFO Flow control thresholds */
> +static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv)
> +{
> + int port, val;
> +
> + /* Port 0: maximum speed -10Gb/s port
> + * required by spec RX FIFO threshold 9KB
> + * Port 1: maximum speed -5Gb/s port
> + * required by spec RX FIFO threshold 4KB
> + * Port 2: maximum speed -1Gb/s port
> + * required by spec RX FIFO threshold 2KB
> + */
> +
> + /* Without loopback port */
> + for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) {
> + if (port == 0) {
> + val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
> + << MVPP2_RX_FC_TRSH_OFFS;
> + val &= MVPP2_RX_FC_TRSH_MASK;
> + mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
> + } else if (port == 1) {
> + val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
> + << MVPP2_RX_FC_TRSH_OFFS;
> + val &= MVPP2_RX_FC_TRSH_MASK;
> + mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
> + } else {
> + val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
> + << MVPP2_RX_FC_TRSH_OFFS;
> + val &= MVPP2_RX_FC_TRSH_MASK;
> + mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
> + }
> + }
> +}
> +
> +/* Configure Rx FIFO Flow control thresholds */
> +void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en)
> +{
> + int val;
> +
> + val = mvpp2_read(priv, MVPP2_RX_FC_REG(port));
> +
> + if (en)
> + val |= MVPP2_RX_FC_EN;
> + else
> + val &= ~MVPP2_RX_FC_EN;
> +
> + mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
> +}
> +
> static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
> {
> int threshold = MVPP2_TX_FIFO_THRESHOLD(size);
> @@ -7156,6 +7207,8 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
> } else {
> mvpp22_rx_fifo_init(priv);
> mvpp22_tx_fifo_init(priv);
> + if (priv->hw_version == MVPP23)
> + mvpp23_rx_fifo_fc_set_tresh(priv);
> }
>
> if (priv->hw_version == MVPP21)
> --
> 1.9.1
>
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