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Message-ID: <20210204135616.GL2789116@dell>
Date:   Thu, 4 Feb 2021 13:56:16 +0000
From:   Lee Jones <lee.jones@...aro.org>
To:     Hans de Goede <hdegoede@...hat.com>
Cc:     Cezary Rojewski <cezary.rojewski@...el.com>,
        Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>,
        Liam Girdwood <liam.r.girdwood@...ux.intel.com>,
        Jie Yang <yang.jie@...ux.intel.com>,
        Mark Brown <broonie@...nel.org>, patches@...nsource.cirrus.com,
        linux-kernel@...r.kernel.org,
        Andy Shevchenko <andy.shevchenko@...il.com>,
        Charles Keepax <ckeepax@...nsource.cirrus.com>,
        alsa-devel@...a-project.org
Subject: Re: [PATCH v4 4/5] ASoC: Intel: Add DMI quirk table to
 soc_intel_is_byt_cr()
On Wed, 20 Jan 2021, Hans de Goede wrote:
> Some Bay Trail systems:
> 1. Use a non CR version of the Bay Trail SoC
> 2. Contain at least 6 interrupt resources so that the
>    platform_get_resource(pdev, IORESOURCE_IRQ, 5) check to workaround
>    non CR systems which list their IPC IRQ at index 0 despite being
>    non CR does not work
> 3. Despite 1. and 2. still have their IPC IRQ at index 0 rather then 5
> 
> Add a DMI quirk table to check for the few known models with this issue,
> so that the right IPC IRQ index is used on these systems.
> 
> Reviewed-by: Andy Shevchenko <andy.shevchenko@...il.com>
> Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
> Signed-off-by: Hans de Goede <hdegoede@...hat.com>
> ---
>  sound/soc/intel/common/soc-intel-quirks.h | 25 +++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
Applied, thanks.
-- 
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
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