linux-kernel - Re: [PATCH 2/9] perf tools: Support the auxiliary event

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <238b21d6-a32c-53d7-b498-b7c6e14a4974@linux.intel.com>
Date:   Fri, 5 Feb 2021 10:45:35 -0500
From:   "Liang, Kan" <kan.liang@...ux.intel.com>
To:     Arnaldo Carvalho de Melo <acme@...nel.org>
Cc:     Namhyung Kim <namhyung@...nel.org>, Ingo Molnar <mingo@...nel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Stephane Eranian <eranian@...gle.com>,
        Jiri Olsa <jolsa@...hat.com>, Andi Kleen <ak@...ux.intel.com>,
        Yao Jin <yao.jin@...ux.intel.com>, maddy@...ux.vnet.ibm.com
Subject: Re: [PATCH 2/9] perf tools: Support the auxiliary event



On 2/5/2021 10:26 AM, Arnaldo Carvalho de Melo wrote:
> Em Fri, Feb 05, 2021 at 09:13:34AM -0500, Liang, Kan escreveu:
>>
>>
>> On 2/5/2021 5:52 AM, Namhyung Kim wrote:
>>> On Wed, Feb 3, 2021 at 5:14 AM <kan.liang@...ux.intel.com> wrote:
>>>>
>>>> From: Kan Liang <kan.liang@...ux.intel.com>
>>>>
>>>> On the Intel Sapphire Rapids server, an auxiliary event has to be
>>>> enabled simultaneously with the load latency event to retrieve complete
>>>> Memory Info.
>>>>
>>>> Add X86 specific perf_mem_events__name() to handle the auxiliary event.
>>>> - Users are only interested in the samples of the mem-loads event.
>>>>     Sample read the auxiliary event.
>>>> - The auxiliary event must be in front of the load latency event in a
>>>>     group. Assume the second event to sample if the auxiliary event is the
>>>>     leader.
>>>> - Add a weak is_mem_loads_aux_event() to check the auxiliary event for
>>>>     X86. For other ARCHs, it always return false.
>>>>
>>>> Parse the unique event name, mem-loads-aux, for the auxiliary event.
>>>>
>>>> Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
>>>> ---
>>>>    tools/perf/arch/x86/util/Build        |  1 +
>>>>    tools/perf/arch/x86/util/mem-events.c | 44 +++++++++++++++++++++++++++++++++++
>>>>    tools/perf/util/evsel.c               |  3 +++
>>>>    tools/perf/util/mem-events.c          |  5 ++++
>>>>    tools/perf/util/mem-events.h          |  2 ++
>>>>    tools/perf/util/parse-events.l        |  1 +
>>>>    tools/perf/util/record.c              |  5 +++-
>>>>    7 files changed, 60 insertions(+), 1 deletion(-)
>>>>    create mode 100644 tools/perf/arch/x86/util/mem-events.c
>>>>
>>>> diff --git a/tools/perf/arch/x86/util/Build b/tools/perf/arch/x86/util/Build
>>>> index 347c39b..d73f548 100644
>>>> --- a/tools/perf/arch/x86/util/Build
>>>> +++ b/tools/perf/arch/x86/util/Build
>>>> @@ -6,6 +6,7 @@ perf-y += perf_regs.o
>>>>    perf-y += topdown.o
>>>>    perf-y += machine.o
>>>>    perf-y += event.o
>>>> +perf-y += mem-events.o
>>>>
>>>>    perf-$(CONFIG_DWARF) += dwarf-regs.o
>>>>    perf-$(CONFIG_BPF_PROLOGUE) += dwarf-regs.o
>>>> diff --git a/tools/perf/arch/x86/util/mem-events.c b/tools/perf/arch/x86/util/mem-events.c
>>>> new file mode 100644
>>>> index 0000000..11b8469
>>>> --- /dev/null
>>>> +++ b/tools/perf/arch/x86/util/mem-events.c
>>>> @@ -0,0 +1,44 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +#include "util/pmu.h"
>>>> +#include "map_symbol.h"
>>>> +#include "mem-events.h"
>>>> +
>>>> +static char mem_loads_name[100];
>>>> +static bool mem_loads_name__init;
>>>> +
>>>> +#define MEM_LOADS_AUX          0x8203
>>>> +#define MEM_LOADS_AUX_NAME     "{cpu/mem-loads-aux/,cpu/mem-loads,ldlat=%u/pp}:S"
>>>> +
>>>> +bool is_mem_loads_aux_event(struct evsel *leader)
>>>> +{
>>>> +       if (!pmu_have_event("cpu", "mem-loads-aux"))
>>>> +               return false;
>>>> +
>>>> +       return leader->core.attr.config == MEM_LOADS_AUX;
>>>> +}
>>>> +
>>>> +char *perf_mem_events__name(int i)
>>>> +{
>>>> +       struct perf_mem_event *e = perf_mem_events__ptr(i);
>>>> +
>>>> +       if (!e)
>>>> +               return NULL;
>>>> +
>>>> +       if (i == PERF_MEM_EVENTS__LOAD) {
>>>> +               if (mem_loads_name__init)
>>>> +                       return mem_loads_name;
>>>> +
>>>> +               mem_loads_name__init = true;
>>>> +
>>>> +               if (pmu_have_event("cpu", "mem-loads-aux")) {
>>>> +                       scnprintf(mem_loads_name, sizeof(MEM_LOADS_AUX_NAME),
>>>> +                                 MEM_LOADS_AUX_NAME, perf_mem_events__loads_ldlat);
>>>
>>> It changes "%u" to an actual latency value, right?
>>> What if the value takes 3 or more digits?
>>> I'm not sure scnprintf() will handle it properly.
>>>
>>
>> Yes, you are right. We should use the sizeof(mem_loads_name) as below.
>> I will submit a patch to fix it.
>>
>> diff --git a/tools/perf/arch/x86/util/mem-events.c
>> b/tools/perf/arch/x86/util/mem-events.c
>> index 11b8469..588110f 100644
>> --- a/tools/perf/arch/x86/util/mem-events.c
>> +++ b/tools/perf/arch/x86/util/mem-events.c
>> @@ -31,7 +31,7 @@ char *perf_mem_events__name(int i)
>>   		mem_loads_name__init = true;
>>
>>   		if (pmu_have_event("cpu", "mem-loads-aux")) {
>> -			scnprintf(mem_loads_name, sizeof(MEM_LOADS_AUX_NAME),
>> +			scnprintf(mem_loads_name, sizeof(mem_loads_name),
>>   				  MEM_LOADS_AUX_NAME, perf_mem_events__loads_ldlat);
>>   		} else {
>>   			scnprintf(mem_loads_name, sizeof(mem_loads_name),
> 
> I'll fold this in the relevant cset.
> 

Thanks!

Kan