linux-kernel - Re: [PATCH v9 net-next 01/15] doc: marvell: add CM3 address space and PPv2.3 description

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Date:   Sun, 7 Feb 2021 22:30:03 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     stefanc@...vell.com
Cc:     netdev@...r.kernel.org, thomas.petazzoni@...tlin.com,
        davem@...emloft.net, nadavh@...vell.com, ymarkman@...vell.com,
        linux-kernel@...r.kernel.org, kuba@...nel.org,
        linux@...linux.org.uk, mw@...ihalf.com, rmk+kernel@...linux.org.uk,
        atenart@...nel.org, devicetree@...r.kernel.org, robh+dt@...nel.org,
        sebastian.hesselbarth@...il.com, gregory.clement@...tlin.com,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v9 net-next 01/15] doc: marvell: add CM3 address space
 and PPv2.3 description

On Sun, Feb 07, 2021 at 08:38:43PM +0200, stefanc@...vell.com wrote:
> From: Stefan Chulski <stefanc@...vell.com>
> 
> Patch adds CM3 address space PPv2.3 description.
> 
> Signed-off-by: Stefan Chulski <stefanc@...vell.com>
> ---
>  Documentation/devicetree/bindings/net/marvell-pp2.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt b/Documentation/devicetree/bindings/net/marvell-pp2.txt
> index b783976..1eb480a 100644
> --- a/Documentation/devicetree/bindings/net/marvell-pp2.txt
> +++ b/Documentation/devicetree/bindings/net/marvell-pp2.txt
> @@ -1,5 +1,6 @@
>  * Marvell Armada 375 Ethernet Controller (PPv2.1)
>    Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
> +  Marvell CN913X Ethernet Controller (PPv2.3)
>  
>  Required properties:
>  
> @@ -12,7 +13,7 @@ Required properties:
>  	- common controller registers
>  	- LMS registers
>  	- one register area per Ethernet port
> -  For "marvell,armada-7k-pp2", must contain the following register
> +  For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the following register
>    sets:
>  	- packet processor registers
>  	- networking interfaces registers

Hi Stefan

Shouldn't there be an entry here describing what the third register
set is?