linux-kernel - Re: [PATCH] MIPS: Make check condition for SDBBP consistent with EJTAG spec

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Message-Id: <76dbc72a-32fd-4de3-bc36-3eb0d0eebb44@www.fastmail.com>
Date:   Tue, 09 Feb 2021 00:32:49 +0800
From:   "Jiaxun Yang" <jiaxun.yang@...goat.com>
To:     "Tiezhu Yang" <yangtiezhu@...ngson.cn>,
        "Thomas Bogendoerfer" <tsbogend@...ha.franken.de>
Cc:     "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
        linux-kernel@...r.kernel.org, "Xuefeng Li" <lixuefeng@...ngson.cn>
Subject: Re: [PATCH] MIPS: Make check condition for SDBBP consistent with EJTAG spec



On Mon, Feb 8, 2021, at 9:14 PM, Tiezhu Yang wrote:
> According to MIPS EJTAG Specification [1], a Debug Breakpoint
> exception occurs when an SDBBP instruction is executed, the
> CP0_DEBUG bit DBp indicates that a Debug Breakpoint exception
> occurred, just check bit DBp for SDBBP is more accurate.
> 
> [1] http://www.t-es-t.hu/download/mips/md00047f.pdf
> 
> Signed-off-by: Tiezhu Yang <yangtiezhu@...ngson.cn>
> ---
>  arch/mips/kernel/genex.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
> index bcce32a..6336826 100644
> --- a/arch/mips/kernel/genex.S
> +++ b/arch/mips/kernel/genex.S
> @@ -349,8 +349,8 @@ NESTED(ejtag_debug_handler, PT_SIZE, sp)
>  	MTC0	k0, CP0_DESAVE
>  	mfc0	k0, CP0_DEBUG
>  
> -	sll	k0, k0, 30	# Check for SDBBP.
> -	bgez	k0, ejtag_return
> +	andi	k0, k0, 0x2	# Check for SDBBP.
> +	beqz	k0, ejtag_return

You'd better define a marco for it to prevent further confusion.

Btw I'm curious about how do kernel receive EJTAG exception?
In my understanding there are only two possible EJTAG exception vectors,
0xbfc00480 and DSEG one. Both of them are reachable by kernel.
How do this piece of code work?

Thanks.

- Jiaxun

>  
>  #ifdef CONFIG_SMP
>  1:	PTR_LA	k0, ejtag_debug_buffer_spinlock
> -- 
> 2.1.0
> 
>

-- 
- Jiaxun