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Message-ID: <161280857580.76967.14422472309861573115@swboyd.mtv.corp.google.com>
Date: Mon, 08 Feb 2021 10:22:55 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>,
linux-arm-msm@...r.kernel.org
Cc: konrad.dybcio@...ainline.org, marijn.suijten@...ainline.org,
martin.botka@...ainline.org, phone-devel@...r.kernel.org,
linux-kernel@...r.kernel.org, agross@...nel.org,
bjorn.andersson@...aro.org, mturquette@...libre.com,
robh+dt@...nel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>
Subject: Re: [PATCH v2 11/11] clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:59)
> The GPU PLL0 is not a fixed PLL and the rate can be set on it:
> this is necessary especially on boards which bootloader is setting
> a very low rate on this PLL before booting Linux, which would be
> unsuitable for postdividing to reach the maximum allowed Adreno GPU
> frequency of 710MHz (or, actually, even 670MHz..) on this SoC.
>
> To allow setting rates on the GPU PLL0, also define VCO boundaries
> and set the CLK_SET_RATE_PARENT flag to the GPU PLL0 postdivider.
>
> With this change, the Adreno GPU is now able to scale through all
> the available frequencies.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
> ---
Applied to clk-next
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