linux-kernel - Re: [PATCH v7 02/14] clk: tegra: Don't enable PLLE HW sequencer at init

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Message-ID: <161281252000.76967.4881086496669699756@swboyd.mtv.corp.google.com>
Date:   Mon, 08 Feb 2021 11:28:40 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     JC Kuo <jckuo@...dia.com>, gregkh@...uxfoundation.org,
        jonathanh@...dia.com, kishon@...com, mturquette@...libre.com,
        robh@...nel.org, thierry.reding@...il.com
Cc:     linux-tegra@...r.kernel.org, linux-usb@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        nkristam@...dia.com, linux-clk@...r.kernel.org,
        JC Kuo <jckuo@...dia.com>, Thierry Reding <treding@...dia.com>
Subject: Re: [PATCH v7 02/14] clk: tegra: Don't enable PLLE HW sequencer at init

Quoting JC Kuo (2021-01-19 23:34:02)
> PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
> power sequencers' output to enable/disable PLLE. PLLE hardware power
> sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
> are enabled.
> 
> Signed-off-by: JC Kuo <jckuo@...dia.com>
> Acked-by: Thierry Reding <treding@...dia.com>
> ---

Acked-by: Stephen Boyd <sboyd@...nel.org>