linux-kernel - Re: [PATCH v10 net-next 03/15] net: mvpp2: add CM3 SRAM memory map

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Message-ID: <CAPv3WKfjnkAt7=cb-_90n5xziQnkunyCxfu7LHQ-RE1W_fc9bg@mail.gmail.com>
Date:   Mon, 8 Feb 2021 09:45:53 +0100
From:   Marcin Wojtas <mw@...ihalf.com>
To:     Stefan Chulski <stefanc@...vell.com>
Cc:     netdev <netdev@...r.kernel.org>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        "David S. Miller" <davem@...emloft.net>, nadavh@...vell.com,
        Yan Markman <ymarkman@...vell.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Jakub Kicinski <kuba@...nel.org>,
        Russell King - ARM Linux <linux@...linux.org.uk>,
        Andrew Lunn <andrew@...n.ch>,
        Russell King <rmk+kernel@...linux.org.uk>, atenart@...nel.org,
        devicetree@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        Grégory Clement <gregory.clement@...tlin.com>,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v10 net-next 03/15] net: mvpp2: add CM3 SRAM memory map

Hi,

pon., 8 lut 2021 o 09:33 <stefanc@...vell.com> napisał(a):
>
> From: Stefan Chulski <stefanc@...vell.com>
>
> This patch adds CM3 memory map and CM3 read/write callbacks.

The read/write callbacks are not added in this patch, please correct
the commit message.

Best regards,
Marcin

>
> Signed-off-by: Stefan Chulski <stefanc@...vell.com>
> Reviewed-by: Andrew Lunn <andrew@...n.ch>
> ---
>  drivers/net/ethernet/marvell/mvpp2/mvpp2.h      |  1 +
>  drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 26 ++++++++++++++++++++
>  2 files changed, 27 insertions(+)
>
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> index 6bd7e40..56e90ab 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> @@ -925,6 +925,7 @@ struct mvpp2 {
>         /* Shared registers' base addresses */
>         void __iomem *lms_base;
>         void __iomem *iface_base;
> +       void __iomem *cm3_base;
>
>         /* On PPv2.2, each "software thread" can access the base
>          * register through a separate address space, each 64 KB apart
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> index a07cf60..eec3796 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> @@ -6846,6 +6846,27 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
>         return 0;
>  }
>
> +static int mvpp2_get_sram(struct platform_device *pdev,
> +                         struct mvpp2 *priv)
> +{
> +       struct resource *res;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> +       if (!res) {
> +               if (has_acpi_companion(&pdev->dev))
> +                       dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n");
> +               else
> +                       dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n");
> +               return 0;
> +       }
> +
> +       priv->cm3_base = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(priv->cm3_base))
> +               return PTR_ERR(priv->cm3_base);
> +
> +       return 0;
> +}
> +
>  static int mvpp2_probe(struct platform_device *pdev)
>  {
>         const struct acpi_device_id *acpi_id;
> @@ -6902,6 +6923,11 @@ static int mvpp2_probe(struct platform_device *pdev)
>                 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
>                 if (IS_ERR(priv->iface_base))
>                         return PTR_ERR(priv->iface_base);
> +
> +               /* Map CM3 SRAM */
> +               err = mvpp2_get_sram(pdev, priv);
> +               if (err)
> +                       dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
>         }
>
>         if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
> --
> 1.9.1
>