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Message-ID: <161285690197.418021.15554726449883492168@swboyd.mtv.corp.google.com>
Date:   Mon, 08 Feb 2021 23:48:21 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     <pawel.mikolaj.chmiel@...il.com>, kgene@...nel.org,
        krzk@...nel.org, mturquette@...libre.com
Cc:     s.nawrocki@...sung.com, tomasz.figa@...il.com,
        cw00.choi@...sung.com, linux-samsung-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, <pawel.mikolaj.chmiel@...il.com>
Subject: Re: [PATCH v3] clk: exynos7: Keep aclk_fsys1_200 enabled

Quoting (2021-01-31 09:04:28)
> This clock must be always enabled to allow access to any registers in
> fsys1 CMU. Until proper solution based on runtime PM is applied
> (similar to what was done for Exynos5433), fix this by calling
> clk_prepare_enable() directly from clock provider driver.
> 
> It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
> UFS module is probed before pmic used to power that device.
> In this case defer probe was happening and that clock was disabled by
> UFS driver, causing whole boot to hang on next CMU access.
> 

Does this need a Fixes tag?

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