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Message-ID: <eae79cc3-f857-d39e-5257-c6aa263eaf07@somainline.org>
Date: Tue, 9 Feb 2021 14:19:37 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>
To: Stephen Boyd <sboyd@...nel.org>, linux-arm-msm@...r.kernel.org
Cc: konrad.dybcio@...ainline.org, marijn.suijten@...ainline.org,
martin.botka@...ainline.org, phone-devel@...r.kernel.org,
linux-kernel@...r.kernel.org, agross@...nel.org,
bjorn.andersson@...aro.org, mturquette@...libre.com,
robh+dt@...nel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v2 07/11] clk: qcom: mmcc-msm8998: Set
CLK_GET_RATE_NOCACHE to pixel/byte clks
Il 08/02/21 19:21, Stephen Boyd ha scritto:
> Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:55)
>> The pixel and byte clocks rate should not be cached, as a VCO shutdown
>> may clear the frequency setup and this may not be set again due to the
>> cached rate being present.
>> This will also be useful when shadow clocks will be implemented in
>> the DSI PLL for seamless timing/resolution switch.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
>> ---
>> drivers/clk/qcom/mmcc-msm8998.c | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> We didn't do this on sdm845, so I'm not going to apply this patch. The
> rate caching thing is a problem with the display driver that should be
> fixed some other way vs. setting nocache here.
>
Ok, I agree.
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