lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-Id: <161296139640.22133.12504586706777255696.b4-ty@arm.com>
Date:   Wed, 10 Feb 2021 12:52:33 +0000
From:   Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To:     tjoseph@...ence.com, linux-pci@...r.kernel.org, kishon@...com,
        bhelgaas@...gle.com, robh@...nel.org, linux-kernel@...r.kernel.org,
        Nadeem Athani <nadeem@...ence.com>
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>, mparab@...ence.com,
        pthombar@...ence.com, sjakhade@...ence.com
Subject: Re: [PATCH v8 0/2] PCI: cadence: Retrain Link to work around Gen2

On Tue, 9 Feb 2021 15:46:20 +0100, Nadeem Athani wrote:
> Cadence controller will not initiate autonomous speed change if strapped
> as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
> Adding a quirk flag for defective IP. In future IP revisions this will not
> be applicable.
> 
> Version history:
> Changes in v8:
> - Adding a new function cdns_pcie_host_start_link().
> Changes in v7:
> - Changing the commit title of patch 1 in this series.
> - Added a return value for function cdns_pcie_retrain().
> Changes in v6:
> - Move the position of function cdns_pcie_host_wait_for_link to remove
>   compilation error. No changes in code. Separate patch for this.
> Changes in v5:
> - Remove the compatible string based setting of quirk flag.
> - Removed additional Link Up Check
> - Removed quirk from pcie-cadence-plat.c and added in pci-j721e.c
> Changes in v4:
> - Added a quirk flag based on a new compatible string.
> - Change of api for link up: cdns_pcie_host_wait_for_link().
> Changes in v3:
> - To set retrain link bit,checking device capability & link status.
> - 32bit read in place of 8bit.
> - Minor correction in patch comment.
> - Change in variable & macro name.
> Changes in v2:
> - 16bit read in place of 8bit.
> 
> [...]

Applied to pci/cadence, squashed two commits together since it makes
no sense to keep them separate. Also, please check:

git log --oneline

when writing patches to keep the changes uniform, I had to edit your
commit.

Thanks,
Lorenzo

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ