linux-kernel - [tip: perf/core] perf/x86/rapl: Add msr mask support

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Date:   Wed, 10 Feb 2021 13:59:30 -0000
From:   "tip-bot2 for Zhang Rui" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Zhang Rui <rui.zhang@...el.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>,
        Andi Kleen <ak@...ux.intel.com>, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: [tip: perf/core] perf/x86/rapl: Add msr mask support

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     ffb20c2e52e8709b5fc9951e8863e31efb1f2cba
Gitweb:        https://git.kernel.org/tip/ffb20c2e52e8709b5fc9951e8863e31efb1f2cba
Author:        Zhang Rui <rui.zhang@...el.com>
AuthorDate:    Fri, 05 Feb 2021 00:18:14 +08:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Wed, 10 Feb 2021 14:44:54 +01:00

perf/x86/rapl: Add msr mask support

In some cases, when probing a perf MSR, we're probing certain bits of the
MSR instead of the whole register, thus only these bits should be checked.

For example, for RAPL ENERGY_STATUS MSR, only the lower 32 bits represents
the energy counter, and the higher 32bits are reserved.

Introduce a new mask field in struct perf_msr to allow probing certain
bits of a MSR.

This change is transparent to the current perf_msr_probe() users.

Signed-off-by: Zhang Rui <rui.zhang@...el.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Reviewed-by: Andi Kleen <ak@...ux.intel.com>
Link: https://lkml.kernel.org/r/20210204161816.12649-1-rui.zhang@intel.com
---
 arch/x86/events/probe.c | 7 ++++++-
 arch/x86/events/probe.h | 7 ++++---
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/x86/events/probe.c b/arch/x86/events/probe.c
index 136a1e8..600bf8d 100644
--- a/arch/x86/events/probe.c
+++ b/arch/x86/events/probe.c
@@ -28,6 +28,7 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data)
 	for (bit = 0; bit < cnt; bit++) {
 		if (!msr[bit].no_check) {
 			struct attribute_group *grp = msr[bit].grp;
+			u64 mask;
 
 			/* skip entry with no group */
 			if (!grp)
@@ -44,8 +45,12 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data)
 			/* Virt sucks; you cannot tell if a R/O MSR is present :/ */
 			if (rdmsrl_safe(msr[bit].msr, &val))
 				continue;
+
+			mask = msr[bit].mask;
+			if (!mask)
+				mask = ~0ULL;
 			/* Disable zero counters if requested. */
-			if (!zero && !val)
+			if (!zero && !(val & mask))
 				continue;
 
 			grp->is_visible = NULL;
diff --git a/arch/x86/events/probe.h b/arch/x86/events/probe.h
index 4c8e0af..261b9bd 100644
--- a/arch/x86/events/probe.h
+++ b/arch/x86/events/probe.h
@@ -4,10 +4,11 @@
 #include <linux/sysfs.h>
 
 struct perf_msr {
-	u64			  msr;
-	struct attribute_group	 *grp;
+	u64			msr;
+	struct attribute_group	*grp;
 	bool			(*test)(int idx, void *data);
-	bool			  no_check;
+	bool			no_check;
+	u64			mask;
 };
 
 unsigned long