linux-kernel - Re: [PATCH 1/2] dt-bindings: mailbox: omap: Update binding for AM64x SoCs

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Message-ID: <dd0c9946-06fd-2c61-b8a4-67b72287ab90@ti.com>
Date:   Tue, 9 Feb 2021 13:26:10 -0600
From:   Suman Anna <s-anna@...com>
To:     Rob Herring <robh@...nel.org>
CC:     Jassi Brar <jassisinghbrar@...il.com>,
        <devicetree@...r.kernel.org>, <linux-omap@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] dt-bindings: mailbox: omap: Update binding for AM64x
 SoCs

On 2/9/21 1:24 PM, Rob Herring wrote:
> On Wed, Jan 27, 2021 at 01:55:59PM -0600, Suman Anna wrote:
>> Update the existing OMAP Mailbox binding to include the info for
>> AM64x SoCs. There are some minor IP integration differences between
>> the AM64x SoCs and the previous AM65x and J721E SoC families.
>>
>> Signed-off-by: Suman Anna <s-anna@...com>
>> ---
>>  .../bindings/mailbox/omap-mailbox.txt         | 22 +++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
>> index 5fe80c1c19fc..c993d1a5c14a 100644
>> --- a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
>> +++ b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
>> @@ -28,6 +28,9 @@ SoCs has each of these instances form a cluster and combine multiple clusters
>>  into a single IP block present within the Main NavSS. The interrupt lines from
>>  all these clusters are multiplexed and routed to different processor subsystems
>>  over a limited number of common interrupt output lines of an Interrupt Router.
>> +The AM64x SoCS also uses a single IP block comprising of multiple clusters,
>> +but the number of clusters are smaller, and the interrupt output lines are
>> +connected directly to various processors.
>>  
>>  Mailbox Device Node:
>>  ====================
>> @@ -42,6 +45,7 @@ Required properties:
>>  			    "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
>>  						   AM43xx and DRA7xx SoCs
>>  			    "ti,am654-mailbox" for K3 AM65x and J721E SoCs
>> +			    "ti,am64-mailbox" for K3 AM64x SoCs
>>  - reg:			Contains the mailbox register address range (base
>>  			address and length)
>>  - interrupts:		Contains the interrupt information for the mailbox
>> @@ -178,3 +182,21 @@ mailbox: mailbox@...c8000 {
>>  		};
>>  	};
>>  };
>> +
>> +4. /* AM64x */
>> +&cbass_main {
> 
> Please don't add examples for just a new compatible.

Thanks, will keep this in mind for the future and drop this as well just like on
the HwSpinlock binding update.

regards
Suman

> 
>> +	mailbox0_cluster2: mailbox@...20000 {
>> +		compatible = "ti,am64-mailbox";
>> +		reg = <0x00 0x29020000 0x00 0x200>;
>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
>> +		             <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
>> +		#mbox-cells = <1>;
>> +		ti,mbox-num-users = <4>;
>> +		ti,mbox-num-fifos = <16>;
>> +
>> +		mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
>> +			ti,mbox-rx = <0 0 2>;
>> +			ti,mbox-tx = <1 0 2>;
>> +		};
>> +	};
>> +};
>> -- 
>> 2.29.2
>>