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Date: Thu, 11 Feb 2021 13:09:59 -0500
From: Jonathan Marek <jonathan@...ek.ca>
To: linux-arm-msm@...r.kernel.org
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
DEVICE TREE BINDINGS), linux-kernel@...r.kernel.org (open list)
Subject: [PATCH 2/2] arm64: dts: qcom: sm8250: fix display nodes
Apply these fixes to the newly added sm8250 display ndoes
- Use sm8250 compatibles instead of sdm845 compatibles
- Remove "notused" interconnect (which apparently was blindly copied from
my old patches)
- Use dispcc node example from dt-bindings, removing clocks which aren't
documented or used by the driver and fixing the region size.
Note: also removed the mmcx-supply for dispcc which wasn't documented when
it was added. I would have left it there but it is also breaking my
use-case (setting a lower power level than what the bootloader sets?).
Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Jonathan Marek <jonathan@...ek.ca>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 34 ++++++++--------------------
1 file changed, 9 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 947e1accae3a..20a3ff30e924 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2323,14 +2323,13 @@ usb_2_dwc3: dwc3@...0000 {
};
mdss: mdss@...0000 {
- compatible = "qcom,sdm845-mdss";
+ compatible = "qcom,sm8250-mdss";
reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
- interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>,
- <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
+ interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
<&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
- interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
+ interconnect-names = "mdp0-mem", "mdp1-mem";
power-domains = <&dispcc MDSS_GDSC>;
@@ -2356,7 +2355,7 @@ mdss: mdss@...0000 {
ranges;
mdss_mdp: mdp@...1000 {
- compatible = "qcom,sdm845-dpu";
+ compatible = "qcom,sm8250-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb0000 0 0x2008>;
reg-names = "mdp", "vbif";
@@ -2580,36 +2579,21 @@ opp-358000000 {
dispcc: clock-controller@...0000 {
compatible = "qcom,sm8250-dispcc";
- reg = <0 0x0af00000 0 0x20000>;
- mmcx-supply = <&mmcx_reg>;
+ reg = <0 0x0af00000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
- <0>,
- <0>,
- <0>,
- <0>,
- <0>,
- <0>,
- <0>,
- <0>,
- <&sleep_clk>;
+ <&dp_phy 0>,
+ <&dp_phy 1>;
clock-names = "bi_tcxo",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_byteclk",
"dsi1_phy_pll_out_dsiclk",
- "dp_link_clk_divsel_ten",
- "dp_vco_divided_clk_src_mux",
- "dptx1_phy_pll_link_clk",
- "dptx1_phy_pll_vco_div_clk",
- "dptx2_phy_pll_link_clk",
- "dptx2_phy_pll_vco_div_clk",
- "edp_phy_pll_link_clk",
- "edp_phy_pll_vco_div_clk",
- "sleep_clk";
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
--
2.26.1
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