linux-kernel - Re: [PATCH v6 02/15] clk: tegra: Don't enable PLLE HW sequencer at init

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Date:   Wed, 10 Feb 2021 19:06:17 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     JC Kuo <jckuo@...dia.com>, gregkh@...uxfoundation.org,
        jonathanh@...dia.com, kishon@...com, robh@...nel.org,
        thierry.reding@...il.com
Cc:     linux-tegra@...r.kernel.org, linux-usb@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        nkristam@...dia.com, JC Kuo <jckuo@...dia.com>,
        Thierry Reding <treding@...dia.com>
Subject: Re: [PATCH v6 02/15] clk: tegra: Don't enable PLLE HW sequencer at init

Quoting JC Kuo (2021-01-19 00:55:33)
> PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
> power sequencers' output to enable/disable PLLE. PLLE hardware power
> sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
> are enabled.
> 
> Signed-off-by: JC Kuo <jckuo@...dia.com>
> Acked-by: Thierry Reding <treding@...dia.com>
> ---

Acked-by: Stephen Boyd <sboyd@...nel.org>