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Message-ID: <7016de66-f254-2bd6-ce29-3b44133feaa0@infradead.org>
Date: Wed, 10 Feb 2021 22:23:44 -0800
From: Randy Dunlap <rdunlap@...radead.org>
To: Nava kishore Manne <nava.manne@...inx.com>, mdf@...nel.org,
trix@...hat.com, robh+dt@...nel.org, michal.simek@...inx.com,
linux-fpga@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
chinnikishore369@...il.com
Cc: git@...inx.com,
Appana Durga Kedareswara rao <appana.durga.rao@...inx.com>
Subject: Re: [PATCH v2 3/3] fpga: versal-fpga: Add versal fpga manager driver
Hi--
On 2/10/21 10:05 PM, Nava kishore Manne wrote:
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index bf85b9a65ec2..dcd2ed5a7956 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -223,4 +223,12 @@ config FPGA_MGR_ZYNQMP_FPGA
> to configure the programmable logic(PL) through PS
> on ZynqMP SoC.
>
> +config FPGA_MGR_VERSAL_FPGA
> + tristate "Xilinx Versal FPGA"
> + depends on ARCH_ZYNQMP || COMPILE_TEST
> + help
> + Select this option to enable FPGA manager driver support for
> + Xilinx Versal SOC. This driver uses the versal soc firmware
How about consistently capitalizing Versal and SOC (above and below)?
> + interface to load programmable logic(PL) images
> + on versal soc.
> endif # FPGA
thanks.
--
~Randy
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