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Date:   Thu, 11 Feb 2021 12:20:48 +0100
From:   Marek Vasut <marex@...x.de>
To:     Frieder Schrempf <frieder.schrempf@...tron.de>,
        Claudius Heine <ch@...x.de>, Rob Herring <robh+dt@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] pinctrl: imx: imx8mm: fix pad offset of SD1_DATA0 pin

On 2/11/21 11:17 AM, Frieder Schrempf wrote:
> On 11.02.21 10:54, Claudius Heine wrote:
>> There is a 0 missing in the pad register offset. This patch adds it.
>>
>> Signed-off-by: Claudius Heine <ch@...x.de>
> 
> I think this should rather be prefixed by "arm64: dts: imx8mm:" as this 
> is no change in the pinctrl driver, but only in the devicetree.
> 
> And I guess this deserves a "Fixes" and "Cc: stable" tag, so:
> 
> Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for 
> imx8mm")
> Cc: stable@...r.kernel.org
> Reviewed-by: Frieder Schrempf <frieder.schrempf@...tron.de>

Indeed.

But since this isn't the first such fix, I wonder whether it wouldn't be 
a good idea to regenerate those pinctrl tables and see whether there are 
any other such issues in them. I wonder, is there some sort of register 
and bit list in machine-parseable form for the MX8M ?

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